XCore 200 USB Port Usage

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
bearcat
Respected Member
Posts: 259
Joined: Fri Mar 19, 2010 4:49 am

XCore 200 USB Port Usage

Postby bearcat » Wed Apr 19, 2017 12:59 am

Searched, couldn't find another thread.

Found different port usages (XU216-512-TQ128 datasheet):
Image

From the USB Library v3.1.2 (these 1 bit ports are confusing to me):
Image

I had wanted to use P1A0, until I found the above mention. I am using Tile1 for the usb_tile.

Thanks
mon2
XCore Expert
Posts: 646
Joined: Thu Jun 10, 2010 11:43 am
Contact:

Postby mon2 » Wed Apr 19, 2017 4:02 am

Hi bearcat. I will try to clarify.

1) P1A0 is linked to the physical pin on the XMOS CPU with label X0D00. See your CPU datasheet to locate the physical port pin X0D00. The prefix "X0" identifies the port pin to belong to tile # 0. So if the port pin(s) has a "X1" prefix, the port pin(s) are linked to tile # 1 and so on...

XMOS offers different devices with multiple tiles.

2) Now on the USB interface. The USB block offers the port names with widths which become bonded to the USB PHY interface and only if the USB interface is enabled. Respectively, the port pins that will actually get routed will be on the tile that you define. You noted tile # 1 for the USB function so this means, review the USB internal diagram and note that:

Port_8A = 8 bit port block "A" on tile # 1 is now off limits for your project because this block has been routed to the USB function.
Port_1K = 1 bit port block "K" on tile # 1 is now off limits for your project because this block has been routed to the USB function.
Port_1H = 1 bit port block "H" on tile # 1 is now off limits for your project because this block has been routed to the USB function.

and so on.

The best way to simplify the ideas here is to think of the internal logic that multiplexes the port pins to either some internal function like the USB PHY or Ethernet PHY (some parts have one or both of these features) OR the same port pins are left bonded to the physical pins on the CPU for your bit-banging projects if either auxiliary function is not enabled.

Hope this makes some sense but it is late so write back if there are still any questions and someone will help.
RitchRock
Member++
Posts: 28
Joined: Tue Jan 17, 2017 9:25 pm

Postby RitchRock » Wed Apr 19, 2017 4:29 am

I have been using this document, however it seems there is some discrepancy with the photos you posted. https://www.xmos.com/support/silicon?co ... duct=19424
bearcat
Respected Member
Posts: 259
Joined: Fri Mar 19, 2010 4:49 am

Postby bearcat » Wed Apr 19, 2017 5:01 am

Thanks for the link to the speadsheet. I hadn't ran across that yet. I need to study all those pins and numbers is great detail, to verify my schematic...

I assumed that the ports used by the USB phy when assigned to each tile, would be the same ports for either tile. So Port1E, etc. would be used for whichever tile assigned. I was transposing the port names from the second diagram to tile#1. So that chart was telling me Port1A is used on Tile#0, or Tile#1 (if assigned to USB). Even if I didn't transpose to Tile#1, I didn't understand Port1A usage if assigned to Tile#0.

The spreadsheet matched the diagram from the Part manual.

Just asking if I need to ignore the table from the USB Lib manual.

Thanks all.
matthew1
Member++
Posts: 18
Joined: Mon Oct 19, 2015 2:12 pm

Postby matthew1 » Fri Apr 21, 2017 9:32 am

Hi Bearcat,

I think the USB Library document is incorrect, I have raised this internally. Please refer to the datasheet and the port map spreadsheet.

Regards,

Matthew.
XMOS

Return to “Processors”

Who is online

Users browsing this forum: No registered users and 3 guests