Xlinks with USB on the XU Topic is solved

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
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aneves
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Xlinks with USB on the XU

Postby aneves » Tue Feb 06, 2018 8:07 pm

Hi Everyone!

According to info on this thread:

viewtopic.php?t=6074

We will be able to use the QSPI pins even if the USB PHY is connected to tile 0. Great!

But is the same true for xConnect Links? In other words, if the USB PHY on an XU is connected to tile 0, can we use the links XL3, XL4, and/or XL7 which overlap the ports required by the USB PHY?
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aneves
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Postby aneves » Thu Feb 08, 2018 3:47 pm

Anyone? Can anyone tell me if the xlinks that overlap the USB ports are available after enabling USB on that same tile as is the case with some of the other ports?
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aneves
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Postby aneves » Tue Feb 13, 2018 3:29 pm

Can someone from XMOS please comment? We are spending lots of money trying to develop a product around this platform and at this stage we cannot risk too much time, money, energy and other resources guessing.

Thank you.
avignani
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Postby avignani » Thu Feb 22, 2018 10:30 am

I found exactly the same problem. The ports used by the USB PHY overlap links 4 and 7 (and 3 if you connect it to tile 1). You can only put the PHY on tile 0 and use 2-bit links 0 and 3. Warning: the data sheet shows port 1J used for clock, while the USB driver assigns port 1C to it; who is right? (should be easy to check, were not for the fact that the driver doesn't even compile for XU200!!)

Alberto
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aneves
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Postby aneves » Thu Feb 22, 2018 1:34 pm

Hi avignani,

Are you saying that you were unable to use the links that overlap the ports required by the USB PHY?

It would be great if we could get some insight from XMOS on this one!
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Postby avignani » Thu Feb 22, 2018 7:16 pm

Well, I'm still designing my 4-processor board, I have not the actual hardware and all informations I have come from the data sheet and the compiler warnings; they say you can't use both at the same time.
Nevertheless I will keep the 5-bit links 4 and 7 wired to the chip on the PCB, because I could then define two configurations (without fast links and without USB) and use them as needed, even dynamically; and in my case only one processor is affected. Don't forget that with the USB PHY on tile 0 the links 0 and 3 are available, so connectivity is not completely lost.
I would also like to hear from XMOS on this subject; it is a bit of a mess, they could have used ports E and F instead of A and B, or overlap only the bits 2-4 so to keep the 2-bit link usable...

Alberto
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mon2
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Postby mon2 » Thu Feb 22, 2018 7:42 pm

Hi. Just found this thread.

https://www.xmos.com/published/xcore-20 ... es-portmap

My comments are that the overlapped XLINK ports WILL be available. Based on the above spreadsheet, only the ports with a color background (non-white) will be lost for that group if the USB or RGMII interface is enable as noted by the legend at the top.

The reason for losing these referenced ports is that the internal mux will steer these port pins (non-white background in the spreadsheet) to be used by the enabled USB PHY and/or enabled RGMII interfaces.

The XLINK ports WILL still be available, like the port pins that are with the white background on the noted physical port pins.

That was our understanding when this spreadsheet was first posted and we conducted an afternoon of testing using the port pins. Then we found that the ports with a white background in the spreadsheet are indeed available while the others with a non-white color are lost. Testing was with our XCORE-200 Explorer Kit. Have not confirmed with XLINKS testing but fairly confident they will remain to be available.

Spreadsheet:

White Background color = Good - available
Non-White Background color = Bad (risky as these ports may be disabled) - Danger Will Robinson

However, to be 100% sure, will ping someone at the factory using the batphone on this topic...
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aneves
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Postby aneves » Fri Feb 23, 2018 4:52 pm

Hi mon2,

Thank you very much for your thorough response.

I will wait to hear wait the factory says.

Thanks!!!
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infiniteimprobability
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Postby infiniteimprobability » Mon Feb 26, 2018 5:58 pm

mon2 is completely correct here. For XS2, we connected the PHY to the port logic at the inner end of the pin mux so that the physical pin could still be used *if* there is a port available to connect to it higher in port (or link) precedence. This helps you claw back some of the IO when USB or RGMII is enabled. Our CTO wrote a nice explanation of port precedence here:

viewtopic.php?p=24627#p24627

As you can see from that post, links are the top of the pile (above 1b ports) so will always get the pin above anything else if enabled.
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aneves
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Postby aneves » Wed Feb 28, 2018 7:48 pm

Excellent! Thank you!!

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