XU232 links between nodes configuration

Technical discussions around xCORE processors (e.g. General Purpose (L/G), xCORE-USB, xCORE-Analog, xCORE-XA).
cl-b
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XU232 links between nodes configuration

Postby cl-b » Wed Feb 07, 2018 5:08 pm

Hi,

I cannot find any information on configuring links between node 0 and node 2.
I add the following lines in xn file

Code: Select all

         <Links>
             <Link Encoding="5wire" Delays="2clk">
                   <LinkEndpoint NodeId="0" Link="7"/>
                   <LinkEndpoint NodeId="2" Link="0"/>
              </Link>
              <Link Encoding="5wire" Delays="2clk">
                   <LinkEndpoint NodeId="0" Link="4"/>
                   <LinkEndpoint NodeId="2" Link="3"/>
              </Link>
              <Link Encoding="5wire" Delays="2clk">
                   <LinkEndpoint NodeId="0" Link="6"/>
                   <LinkEndpoint NodeId="2" Link="1"/>
              </Link>
              <Link Encoding="5wire" Delays="2clk">
                   <LinkEndpoint NodeId="0" Link="5"/>
                   <LinkEndpoint NodeId="2" Link="2"/>
              </Link>
            <Link Encoding="5wire">
               <LinkEndpoint NodeId="0" Link="8" Delays="52clk,52clk" />
               <LinkEndpoint NodeId="1" Link="XL0" Delays="1clk,1clk" />
            </Link>
            <Link Encoding="5wire">
               <LinkEndpoint NodeId="2" Link="8" Delays="52clk,52clk" />
               <LinkEndpoint NodeId="3" Link="XL0" Delays="1clk,1clk" />
            </Link>
         </Links>


what are the max and min values for "Delays" ?

Regards

Claire
CousinItt
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Posts: 72
Joined: Wed May 31, 2017 6:55 pm

Postby CousinItt » Thu Feb 08, 2018 9:17 am

All the information should be available already in the appropriate XU232... xn file. When you create a project, check the "Show devices in target selection" box. Or you could just browse the contents of the targets folder in your xTIME composer installation.
cl-b
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Joined: Fri Sep 15, 2017 2:58 pm

Postby cl-b » Thu Feb 08, 2018 10:59 am

In the corresponding xn file Delays is set to "3clk" but I wonder if I can reduce it to 2clk as I have bandwith problem
CousinItt
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Joined: Wed May 31, 2017 6:55 pm

Postby CousinItt » Thu Feb 08, 2018 11:39 am

I would have thought that XMOS would have selected the fastest rate at which the link is stable - they have a vested interest in maximising their performance.

You can do a quick test with the 2clk setting. If it's stable you can check for a performance improvement, and if not something will probably just hang up waiting for the link. Even if it works, there's no guarantee it will be stable over all devices at all temperatures.

If you have bandwidth problems, are you using streaming channels instead of channels or interfaces, to minimise overheads?

By the way, I've been working on a project using two explorer kits with a 5-way link set to 5clk. I did a stability test and it would work down to 2clk but with no reduction in transaction times, presumably because of overheads. The 5 clock setting was a bit arbitrary to start with, but since it was giving the performance I needed and it was clearly reliable, I stuck with it.

Dev
cl-b
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Postby cl-b » Thu Feb 08, 2018 3:16 pm

Thanks for your answer. I try with 2clk delay but it does not seem to be stable.
I cannot use streaming channels because I need at least one bidirectional channel between tile 0 and tile 2 and one bidirectional channel between tile 1 and tile 2.
Transfer chronology :
    - thread_tile2 sends 10 * 32 bits to thread_tile0 and thread_tile0 get 10 * 32 bits from thread_tile2
    - thread_tile2 sends 10 * 32 bits to thread_tile1 and thread_tile1 gets 10 * 32 bits from thread_tile2
    - thread_tile0 sends 10 * 32 bits to thread_tile2 and thread_tile2 gets 10 * 32 bits from thread_tile0
    - thread_tile1 sends 10 * 32 bits to thread_tile2 and thread_tile2 get 10 * 32 bits from thread_tile1

I made some measurement in thread_tile2 :
    - if all the 3 threads are on the same core the whole transfer took 810 ns
    - if thread_tile2 is on the other core the whole transfer took 2300 ns

How to explain such a difference ?
CousinItt
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Joined: Wed May 31, 2017 6:55 pm

Postby CousinItt » Thu Feb 08, 2018 4:57 pm

If all three threads are combined on the same core, maybe the compiler emulates channels. I'm not sure that's what you mean.

If you mean all three are running on the same tile, I think the cores can communicate via channels without going through xconnect. I assume there's an additional overhead for using xconnect.
cl-b
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Joined: Fri Sep 15, 2017 2:58 pm

Postby cl-b » Thu Feb 08, 2018 5:17 pm

Tile 0 and Tile 1 are on the same node (0) and tile 2 is on node 2 (as named in XU232-1024 datasheet).
I could not find information whether there is additional overhead for using xConnect switch between the two nodes.

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