Datasheet Help
Posted: Mon Feb 27, 2012 5:15 pm
Hello guys,
I've been going through a lot of the datasheets for various boards such as the L1 USB Audio board and the XK-1A and had some questions that I cant answer without some more help.
1. On PAGE 2 of the L1 USB Audio Schematic (https://www.xmos.com/download/public/US ... s(1.2).pdf), I noticed that the USB receptacle has 6 pins and I'm confused as to what pins 5 and 6 are. Also the resistor that's connected to both of these pins doesn't have a value and only marked as 'DNP'. Could someone explain this?
2. I noticed that on the XK-1A shematic (PAGE 13/15 in https://www.xmos.com/download/public/XK ... l(1.0).pdf) there isn't a delay on the RST_N pin like I would expect from the minimum requirements so that VDDIO and VDD could come up before RST_N. How is this taken care of?
3. Also on the same schematic, I have no idea why buffers are used in this way. Could someone explain why they are used and why they are used on on the 'TRST_N', 'TMS', 'TCK', and 'RST_N' pins?
4. I've noticed in a lot of schematics tie the MODE(2:3) pins together (XK-1A schematic). However, this creates a problem if you wanted the devices to boot via XLink B. Could someone explain the use of TRST_N on these two pins, does it just idle low when plugged into the board? I'm guessing that the pins are pulled up so that when the JTAG isnt' connected then the device boots from SPI, could someone shed some light on whats actually going on?
5. On the XK-1A schematic, why are two signals multiplexed together? And what is the signal TDOC? I would assume that if the devices were chained together then TDI would go into the device and then TDO from that device would be output to the next so that they could be chained together but TDO is being multiplexed which completely throws me off.
6. In the XS1-L2 example schematic (https://www.xmos.com/published/xs1-l2-1 ... ?support=1) the oscillator that is used is HUGE (ABLS2), is there any reason why this configuration of the oscillator is used as apposed to using something like that used on the XC-1A (Top of Page 2 https://www.xmos.com/published/xs1-l2-1 ... ?support=1)? Are there any constraints on the type of oscillator used or the circuit configuration to make the PLL happy?
7. Ok so this one isn't a question, but I'm pretty sure there is a minor mistake in the datasheet. I noticed that in the XS1-L1 (48pin and 64pin) datasheet, the PLL_AVDD is of type GND and the PLL_AGND is of type PWR which is backward.
If you know an answer could you explain it in as much detail as possible. I've worked with embedded systems but a lot of this is brand new to me, especially interfacing with JTAG. THANK you guys in advance for the help!!
I've been going through a lot of the datasheets for various boards such as the L1 USB Audio board and the XK-1A and had some questions that I cant answer without some more help.
1. On PAGE 2 of the L1 USB Audio Schematic (https://www.xmos.com/download/public/US ... s(1.2).pdf), I noticed that the USB receptacle has 6 pins and I'm confused as to what pins 5 and 6 are. Also the resistor that's connected to both of these pins doesn't have a value and only marked as 'DNP'. Could someone explain this?
2. I noticed that on the XK-1A shematic (PAGE 13/15 in https://www.xmos.com/download/public/XK ... l(1.0).pdf) there isn't a delay on the RST_N pin like I would expect from the minimum requirements so that VDDIO and VDD could come up before RST_N. How is this taken care of?
3. Also on the same schematic, I have no idea why buffers are used in this way. Could someone explain why they are used and why they are used on on the 'TRST_N', 'TMS', 'TCK', and 'RST_N' pins?
4. I've noticed in a lot of schematics tie the MODE(2:3) pins together (XK-1A schematic). However, this creates a problem if you wanted the devices to boot via XLink B. Could someone explain the use of TRST_N on these two pins, does it just idle low when plugged into the board? I'm guessing that the pins are pulled up so that when the JTAG isnt' connected then the device boots from SPI, could someone shed some light on whats actually going on?
5. On the XK-1A schematic, why are two signals multiplexed together? And what is the signal TDOC? I would assume that if the devices were chained together then TDI would go into the device and then TDO from that device would be output to the next so that they could be chained together but TDO is being multiplexed which completely throws me off.
6. In the XS1-L2 example schematic (https://www.xmos.com/published/xs1-l2-1 ... ?support=1) the oscillator that is used is HUGE (ABLS2), is there any reason why this configuration of the oscillator is used as apposed to using something like that used on the XC-1A (Top of Page 2 https://www.xmos.com/published/xs1-l2-1 ... ?support=1)? Are there any constraints on the type of oscillator used or the circuit configuration to make the PLL happy?
7. Ok so this one isn't a question, but I'm pretty sure there is a minor mistake in the datasheet. I noticed that in the XS1-L1 (48pin and 64pin) datasheet, the PLL_AVDD is of type GND and the PLL_AGND is of type PWR which is backward.
If you know an answer could you explain it in as much detail as possible. I've worked with embedded systems but a lot of this is brand new to me, especially interfacing with JTAG. THANK you guys in advance for the help!!