I am noticing on the various dev kits that the SPI flash has additional logic ICs.
Also notice that they vary in the quantity,configuration and type of logic used.
Is there specific documentation about the requirements for using boot flash for each family member of XMOS processors?
I can't find any discussion on design issues related to SPI boot flash. It looks like there is some complexity
and not simply a matter of hooking up the flash pins directly as with other micro controllers.
Also what is the process to create a boot flash file and program it to the flash?
Is their a utility for this in xTimecomposer?
What is SPI boot flash configuration?
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Piker
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sethu_jangala
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The additional logic ICs are used to select the boot mode of the xCORE device. Boot mode is defined by the mode pins that are availabe on the device. Different type of modes are boot from OTP, boot from SPI flash, boot from xCONNECT links. Based on the configuration of the boot mode pins the device boots up. The information is availabe in the devicce data sheet under the section Boot Procedure.
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Piker
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OK thanks.
So if I was rolling my own board could I just use some pullup resistors and jumper headers to set the mode pins?
So if I was rolling my own board could I just use some pullup resistors and jumper headers to set the mode pins?
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infiniteimprobability
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The simple answer is that you can just hook up a SPI flash directly to X0D0, X0D1, X0D10 and X0D11 with just a 10K pullup on CS.
The A8 datasheet has an example of this on page 28
Many of the boards have muxing logic (muxes and latches) so that, after the program has booted, you can have full access to the SPI pins for user use.
One bit ports are a valuable resource on XMOS chips so freeing up SPI after it has booted is sometimes useful. If you have enough pins then just dedicate the ports above to SPI, which is the easiest.
Some of the reference designs (eg. USB audio) multiplex X0D0, X0D10 and X0D11 with other functions such as I2S lines. This is OK, as long as the SPI is de-selected when you use the lines for other purposes, and the other function will not get upset while accessing SPI (and they are not needed simultaenlously!). Again, this is only needed if you are running short of pins and need to double-up
The A8 datasheet has an example of this on page 28
Many of the boards have muxing logic (muxes and latches) so that, after the program has booted, you can have full access to the SPI pins for user use.
One bit ports are a valuable resource on XMOS chips so freeing up SPI after it has booted is sometimes useful. If you have enough pins then just dedicate the ports above to SPI, which is the easiest.
Some of the reference designs (eg. USB audio) multiplex X0D0, X0D10 and X0D11 with other functions such as I2S lines. This is OK, as long as the SPI is de-selected when you use the lines for other purposes, and the other function will not get upset while accessing SPI (and they are not needed simultaenlously!). Again, this is only needed if you are running short of pins and need to double-up