XS1-G4 supercomputing array (with memory)

[DrMario]

Alright, I want you XS1 experts, your opinions. You think I should assign each x8 / x16 SDRAM chips to each of the XS1 CPU cores, totaling up to 4 SDRAM chips for a XS1-G4 chip? You think it's good idea? Or should I be fine with just a SDRAM chip? I have been wondering about assigning each RAM spaces for the cores without slowing them down while doing computationally intense jobs and accessing to the RAMs at the same times.

See "xs1_g4_l2_cache.jpg" image illustration of what I am thinking about implementing the individual SDRAMs for each CPU cores.

[phalt]

This sounds like a rather grand project - can't wait to see some updates about it!

[DrMario]

Thanks for the response. I am going to start on the board for BGA-512 version of XS1-G4 chip (with 16 or 32-bit SDRAM for each cores) - and the Cyclone III FPGA for IO switching and context bridging to the main board.

And, with 8 - 12 layers PCB containing four to eight XS1 chips, it may take a while on KiCAD PCB editor.

[DrMario]

I have been considering a few power supply setup / topologies as they may need to be permanet, soldered on the individual XS1 boards, due to strict limitations on lower Vdd core voltage (1.0 Volts DC), while IO DC rail gets it easier. I may have to get both Vcore and Vio down to 1.0V, so IO crosstalk won't occur too easily.

I have been pondering about PIC-based DC switchmode buck converter, bringing down the 12 Volts DC rail down to 1.0V for XS1-G4 processors (two DC rail voltage - 3.3 V for SDRAM and 128KB Everspin MRAM containing the boot firmware, and 1.0 V for the processors) - I really wanted something more efficient while sipping power from 12 Volts power rail straight outta PC ATX power supply. That on-board SMPS may have to be able of outputting up to 20 Amps for eight XS1-G4 and accompanying chips.