SPI Examples

[jonathan]

Has anyone got any well-commented examples of SPI clock control?

It's another of those where there seem to be a variety of ways to write the interface using a variety of different built-in clock control functions but someone might have the right way - or at least got a well-commented sensibly-parameterised SPI implementation that can be tuned by simply knowing a few details of your target... Or is that too hopeful?

I don't mind rewriting it totally from scratch, but there must be a few implementations kicking around already?

Thanks in advance for any help.

[kster59]

The XMOS SPI sample is pretty general but performance is terrible. It locks out at 300kbits/sec if I remember correctly.

I implemented 50mhz SPI master output for another project after I learned about the joys of serialization.

I can update my version when I have a chance to comment it and clean it up.

[lilltroll]

This might be a general problem:

Some code that is good for basic teaching of the fundamental concept's might be totally crappy to use at high speed. Things should be marked if it's a school book example or if it's optimized for real usages, and if so - optimized for what, speed, memory usages, precision ....

When other vendors releases for an example a signal toolbox it's often asm optimized (believed) to be the fastest possible implementation.

We are not talking about 30% speed increase here, more 3 : 500

[Andy]

The default clock speed for the XMOS SPI example is quite low... I was able to bump it up and get much better performance.

[skoe]

The current version from xmos.com is quite good already and uses clocked output (is it called serialization?). As far as I can see it should be able to run at 50 MHz with the right clock_div.

kster59: Did you mix it up with the UART sample code or does it really fail above 300 kbps?

[stefanharjes]

The XMOS example for spi_master implements mode 3. Can anybody confirm, that with a very small
change of the function 'spi_init' (see below) all four modes can be implemented?

Code: Select all

void spi_init_mode(spi_master_interface &i, int spi_clock_div, unsigned char mode)
{
	// configure ports and clock blocks
	configure_clock_rate(i.blk1, 100, spi_clock_div);
	configure_out_port(i.sclk, i.blk1, 0);
	configure_clock_src(i.blk2, i.sclk);
	configure_out_port(i.mosi, i.blk2, 0);
	configure_in_port(i.miso, i.blk2);

	//phase bit is lsb
       //if not set, do a phase shift (i.e. delay)
	if(!(mode & 0x01)) {
		set_port_sample_delay(i.miso);
		set_port_sample_delay(i.mosi);
	}
	//clock polarity bit is hsb
       //if not set, invert clock polarity
	if(!(mode & 0x02)) set_port_inv(i.sclk);

	clearbuf(i.mosi);
	clearbuf(i.sclk);
	start_clock(i.blk1);
	start_clock(i.blk2);
	i.sclk <: 0xFF;

}

this code contains the following implicit question:
does

Code: Select all

 set_port_sample_delay(port p)

which according to the manual:
changes the sampling edge of a port from 'sample on rising' to 'sample on falling'
also change the writing edge from 'write on falling' to 'write on rising'?

Thanks

Stefan

[Folknology]

this code contains the following implicit question:
does

Code: Select all

set_port_sample_delay(port p)

which according to the manual:
changes the sampling edge of a port from 'sample on rising' to 'sample on falling'
also change the writing edge from 'write on falling' to 'write on rising'?

Unfortunately not Stefan (as far as I know), worth reading through this thread for a earlier conversations around this limitation.

regards
Al