One dummy program have different result ??

[samulasun]

Dear All,

I buy a usb2.0 demo board and try to input 1k sine wave and output it without any change
as below:

Code: Select all

while(1)
        	{
        		audio_in=2;   <------------------------------------------------Please note Here
        		audio_data_out[0]=audio_data[(audio_in-2)];
        		audio_data_out[1]=audio_data[(audio_in-1)];


        		if(audio_in==2)
        			audio_in=0;

				p_i2s_dac <: audio_data_out[0];
				p_lrclk <: 0x80000000;
				p_bclk <: 0xCCCCCCCC;
				p_bclk <: 0xCCCCCCCC;
				p_bclk <: 0xCCCCCCCC;
				p_bclk <: 0xCCCCCCCC;
				p_i2s_adc :> audio_data[audio_in++];

				p_i2s_dac <: audio_data_out[1];
				p_lrclk <: 0x7FFFFFFF;
				p_bclk <: 0xCCCCCCCC;
				p_bclk <: 0xCCCCCCCC;
				p_bclk <: 0xCCCCCCCC;
				p_bclk <: 0xCCCCCCCC;
				p_i2s_adc :> audio_data[audio_in++];
        	}

The strange thing is: if I add "audio_in=2;" then the output audio is correct
(1kHz sine wave as I input), if I cancel this line, the output audio will become noise.
Why??
I can guaranty each time when program run this line the value of audio_in is 2!!
Why this dummy description result in different consequence ??

PS: There are three thread in this L2 chip, First one is main thread, second is 300Hz clock output,
third one is this codec communication.

Please advice, if I miss any important point ??

Thank you all.

[ale500]

Can you please post how did you define the ports ?

What does happen if you only have one thread, the one that outputs the wave ?

[Heater]

The expression:

Code: Select all

audio_data[(audio_in-2)]

Worries me. If audio_in starts out as zero then you are accessing audio_data[-2] which is out of pounds for the array. This I thought should cause some kind of exception and everything stops. or you use #pragma unsafe arrays and get some weird results.

[ale500]

Good catch!... But he says that audio_in is 2, he sets is himself after the while, we do not know what happens before the while.

[samulasun]

Hi all,

Thanks for everyone's concern:

Here is the port setting:

Code: Select all

on stdcore[1] : timer tmr01,tmr02;
on stdcore[1] : out port p4C_led                   		= XS1_PORT_4C;
on stdcore[1] : out port p4D_led                   		= XS1_PORT_4D;
on stdcore[1] : port p_i2c_scl	                                = XS1_PORT_1D;     
on stdcore[1] : port p_i2c_sda	                        = XS1_PORT_1C;
on stdcore[1] : out port p_aud_cfg                         = XS1_PORT_4A;
on stdcore[1] : out port p_pll_clk                            = XS1_PORT_4E;
on stdcore[1] : clock         clk                                   =   XS1_CLKBLK_3 ;
on stdcore[1] : clock    clk_audio_mclk                     = XS1_CLKBLK_1;
on stdcore[1] : clock    clk_audio_bclk                     = XS1_CLKBLK_2; 
on stdcore[1] : out port out_clock         		        = XS1_PORT_1J ;
on stdcore[1] : out port out_P         		        = XS1_PORT_1K ;
on stdcore[1] : buffered out port:32 p_bclk            = XS1_PORT_1I;
on stdcore[1] : buffered out port:32 p_lrclk            = XS1_PORT_1E;
on stdcore[1] : port p_mclk                                     = XS1_PORT_1L;
on stdcore[1] : buffered out port:32 p_i2s_dac      = XS1_PORT_1M;
on stdcore[1] : buffered in port:32 p_i2s_adc         = XS1_PORT_1G;
on stdcore[1] : unsigned audio_data[2];
on stdcore[1] : unsigned audio_data_out[2];

The program in main is as below:

Code: Select all

int main()
{
    par
    {
        on stdcore[1] :
        {
        	int count;
        	unsigned flag01;

        	flag01 = true;
        	configure_clock_rate (clk ,  100 ,   100);
        	configure_out_port (p_pll_clk ,  clk ,  0);
        	configure_port_clock_output ( out_clock ,  clk );
        	start_clock ( clk );

        	p_pll_clk   <:  0  @    count ;         //   timestamped   output

        	while(1)
			{
        		count   +=   1666;
        		p_pll_clk  @    count   <:  1;     //   timed   output
        		count   +=   1666;
        		p_pll_clk  @    count   <:  0;     //   timed   output
			}
        }

        on stdcore[1] :
        {
        	unsigned flag4d,flag1strun=true;
        	unsigned sample_L1,sample_L2,sample_R1,sample_R2;
        	unsigned x;
        	unsigned audio_in=0,audio_out=0;

        	// Codec Initial
        	p_aud_cfg <: 0b1000;
        	I2cRegWrite(0x90, 0x2, 0x01, p_i2c_scl, p_i2c_sda);
        	I2cRegWrite(0x90, 0x4, 0x49, p_i2c_scl, p_i2c_sda);
        	I2cRegWrite(0x90, 0x5, 0x1C, p_i2c_scl, p_i2c_sda);
        	I2cRegWrite(0x90, 0x2, 0x00, p_i2c_scl, p_i2c_sda);
        	// Codec Config
        	I2cRegWrite(0x90, 0x3, 0b11110000, p_i2c_scl, p_i2c_sda);

        	// Config Audio Port
        	configure_clock_src(clk_audio_mclk, p_mclk);
        	configure_out_port_no_ready(p_bclk, clk_audio_mclk, 0);
        	configure_clock_src(clk_audio_bclk, p_bclk);
        	configure_out_port_no_ready(p_i2s_dac, clk_audio_bclk, 0);
       		configure_in_port_no_ready(p_i2s_adc, clk_audio_bclk);
       		configure_out_port_no_ready(p_lrclk, clk_audio_bclk, 0);
       		start_clock(clk_audio_mclk);
       		start_clock(clk_audio_bclk);
       		p_lrclk <: 0x80000000;
       		p_bclk <: 0xCCCCCCCC;
       		p_bclk <: 0xCCCCCCCC;
       		p_bclk <: 0xCCCCCCCC;
       		p_bclk <: 0xCCCCCCCC;
       		p_i2s_adc :> audio_data[audio_in++];

                p_lrclk <: 0x7FFFFFFF;
   		p_bclk <: 0xCCCCCCCC;
   		p_bclk <: 0xCCCCCCCC;
   		p_bclk <: 0xCCCCCCCC;
   		p_bclk <: 0xCCCCCCCC;
   		p_i2s_adc :> audio_data[audio_in++];
   		printstr("codec initial OK");

        	while(1)
        	{
        		audio_in=2; <------------------------------------------Please note here
        		audio_data_out[0]=audio_data[(audio_in-2)];
        		audio_data_out[1]=audio_data[(audio_in-1)];


        		if(audio_in==2)
        			audio_in=0;

				p_i2s_dac <: audio_data_out[0];
				p_lrclk <: 0x80000000;
				p_bclk <: 0xCCCCCCCC;
				p_bclk <: 0xCCCCCCCC;
				p_bclk <: 0xCCCCCCCC;
				p_bclk <: 0xCCCCCCCC;
				p_i2s_adc :> audio_data[audio_in++];

				p_i2s_dac <: audio_data_out[1];
				p_lrclk <: 0x7FFFFFFF;
				p_bclk <: 0xCCCCCCCC;
				p_bclk <: 0xCCCCCCCC;
				p_bclk <: 0xCCCCCCCC;
				p_bclk <: 0xCCCCCCCC;
				p_i2s_adc :> audio_data[audio_in++];
        	}
        }
    }
    return 0;
}

dear Heater and ale500:

The value before while should be 2, I had use a if(audio_in!=2) to catch this
exception, but see nothing.

Please advice how to debug this strange situation. Thank you all.