Hi all,
Today we are publicly releasing sliceKIT, a modular development kit consisting of a Core Board with an L2 on it, together with a range of 6 accessory slices. Our aim is to make it quick and simple to build a wide range of different systems, using the available Slice Cards from XMOS and easily building your own too.
The slices are:
- Audio (4 analog inputs, 4 analog outputs, MIDI, SPDIF output)
- Multi-UART (8 UARTs)
- SDRAM (8 Mbyte)
- 100mb Ethernet
- GPIO (LEDs, buttons, IO expansion + A/D and thermistor)
- Display (480 x 272 full color display. This will be available in the next few weeks)
The Starter Kit includes the Ethernet Slice Card and the GPIO Slice Card, together with the XTAG2 debug adaptor.
Each Slice Card comes with xSOFTip, documentation and a simple demo app to provide an example of how to use it. There are also a number of example applications which make use of a couple of Slice Cards to build a system.
The Starter Kit and Slice cards are all in stock and available at Digikey. We will continue to add more slices, so let us know what you would like to see. All the designs are available online, so it’s easy to build your own slices too – please share your projects and post them on the Projects page!
XCORE members have been involved in this from the beginning, so we’d like to say a big thank you for all your inputs. There are some previous forum posts on sliceKIT here: http://www.xcore.com/forum/viewtopic.ph ... it&start=0
Ali
sliceKIT is here!
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Exciting! I've been following SliceKit discussion on the forums since it started and was just thinking yesterday that there hadn't been any talk about it for a while... and then this!
I'm very interested in developing my own little slices but I can't seem to find details of the connector specifications, such as what signals and port widths are available on the "PCI-e" connectors. I assume up-to-date connector specs and slice core schematics will be released soon.
Does daisy-chaining slice cores disable any of the other four connectors? In any case, I think extension cables allowing slice cores to be stacked would be a very popular accessory.
I'm very interested in developing my own little slices but I can't seem to find details of the connector specifications, such as what signals and port widths are available on the "PCI-e" connectors. I assume up-to-date connector specs and slice core schematics will be released soon.
Does daisy-chaining slice cores disable any of the other four connectors? In any case, I think extension cables allowing slice cores to be stacked would be a very popular accessory.
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Hi TSC the full hardware guide for sliceKIT core board and slices (including designing your own) will be uploaded to the website very soon. I'll post a link here as soon as it is there.
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These might help in the meantime
sliceKIT hardware specs from github
sliceKIT resources page from Xmos.com
regards
Al
sliceKIT hardware specs from github
sliceKIT resources page from Xmos.com
regards
Al
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And it seems the HW guide for sliceKIT is now up:
https://www.xmos.com/node/16091?version=latest
Sorry about the width issues with the vector diagrams - we'll get that sorted out shortly.
https://www.xmos.com/node/16091?version=latest
Sorry about the width issues with the vector diagrams - we'll get that sorted out shortly.
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I saw this in my email this morning, and thought "Wow!" a new 16-core XMOS chip! It must have more RAM as well, and more i/o. Amazing!
And then I realised that the new marketing-speak had lied to me. It was just the L2 processor and you were counting all 8 threads per cpu, so running it at the lowest speed per thread. Don't get me wrong, there's nothing wrong with the L2 apart from the package it comes in, but here's a couple of lessons I've just been taught:
- Raising hopes and then dashing them is never a good idea. If I'd been introduced to the slicekit in a normal way, I'd probably be enthusiastic about it. Now, I'm not interested.
- Even after reading and understanding the new lies-to-customers dictionary, it's still misleading. "Cores" is a terrible way to describe the multithreading capabilites of a CPU, sorry.
Simon.
And then I realised that the new marketing-speak had lied to me. It was just the L2 processor and you were counting all 8 threads per cpu, so running it at the lowest speed per thread. Don't get me wrong, there's nothing wrong with the L2 apart from the package it comes in, but here's a couple of lessons I've just been taught:
- Raising hopes and then dashing them is never a good idea. If I'd been introduced to the slicekit in a normal way, I'd probably be enthusiastic about it. Now, I'm not interested.
- Even after reading and understanding the new lies-to-customers dictionary, it's still misleading. "Cores" is a terrible way to describe the multithreading capabilites of a CPU, sorry.
Simon.
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XMOS, could we have an adapter board for Audio Slice to be used with the XK-1A kit? Like a PCB with a PCI-E x1 (36-pin) slot (http://fi.farnell.com/samtec/pcie-036-0 ... dp/1753906) and two slots for XK-1A Expansion Area compatible IDC connectors. Might be DIYable though but wouldn't cost an arm a leg for XMOS to produce.
Last edited by mhelin on Tue Oct 23, 2012 9:17 pm, edited 1 time in total.
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Some trivial bugs:
--The diagrams are missing from the PDF file.
--It says "Triange" a few times.
--The xsys_detail.svg file is missing.
--l2_core_board.svg is missing.
--It says "XYSY" instead of "XSYS" at least once.
--Square A5 PRSNT SYSTEM PRESENT SIGNAL (ACTIVE LOW) is called
"PRSNT_N" elsewhere.
--In 2.10.5 (the Chain pinout), XLB3i is called XLB0i, and XLA3i is called
XLA4o? The "2b" and "5b" names in that table do not make it clearer.
--Star B11 should be X0D5, not X0D3.
--MSEL on XSYS is what used to be called TRST_N? Is there a document
describing XSYS somewhere? I never saw one.
--"havnig".
--2.10.6 talks about PRSNT_N on the Star slot, but 2.10.1 shows no
such signal.
--Missing closing parenthesis after "Circle + Square".
In the JTAG diagram, SOCKET_10 is Square? And PLUG_00 is Chain?
But then it's not clear to me what XTAG2 in there is. Or what board(s)
the diagram actually shows. But it is clear that it all should just magically
work, yay, present detects are great (if they work) :-)
[EDIT]PLUG_00 is Star, XTAG2 is Chain.
There will also be schematics soon?
I'm quite looking forward to these boards, they seem great so far :-)
--The diagrams are missing from the PDF file.
--It says "Triange" a few times.
--The xsys_detail.svg file is missing.
--l2_core_board.svg is missing.
--It says "XYSY" instead of "XSYS" at least once.
--Square A5 PRSNT SYSTEM PRESENT SIGNAL (ACTIVE LOW) is called
"PRSNT_N" elsewhere.
--In 2.10.5 (the Chain pinout), XLB3i is called XLB0i, and XLA3i is called
XLA4o? The "2b" and "5b" names in that table do not make it clearer.
--Star B11 should be X0D5, not X0D3.
--MSEL on XSYS is what used to be called TRST_N? Is there a document
describing XSYS somewhere? I never saw one.
--"havnig".
--2.10.6 talks about PRSNT_N on the Star slot, but 2.10.1 shows no
such signal.
--Missing closing parenthesis after "Circle + Square".
In the JTAG diagram, SOCKET_10 is Square? And PLUG_00 is Chain?
But then it's not clear to me what XTAG2 in there is. Or what board(s)
the diagram actually shows. But it is clear that it all should just magically
work, yay, present detects are great (if they work) :-)
[EDIT]PLUG_00 is Star, XTAG2 is Chain.
There will also be schematics soon?
I'm quite looking forward to these boards, they seem great so far :-)
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One serious bug:
"The sliceKIT core board features our 16 core L2 device..."
This has to be fixed, all the world is laughing at this double speak. Credibility is being lost.
"The sliceKIT core board features our 16 core L2 device..."
This has to be fixed, all the world is laughing at this double speak. Credibility is being lost.