XMOS today announced xCORE-XA™, eXtended Architecture xCORE device which is a combination of xCORE and low power ARM cortex M3. More information is available here.
Product brief of xCORE-XA is available here.
New xCORE-XA device with ARM Cortex M3
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So it looks as if they have separate memory maps, but communicate via the xconnect switch and I presume AHB on the ARM side, how does that appear on the Arm firmware side, what does the interface look like? From the XS1 side does it work like a Channel/Service interface?
Could I run uClinux on this thing (not that I am suggesting one should) but it sure comes with a good coms stack, can one add external RAM to achieve this?
So many questions..
regards
Al
Could I run uClinux on this thing (not that I am suggesting one should) but it sure comes with a good coms stack, can one add external RAM to achieve this?
So many questions..
regards
Al
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Cool!!! Gimme a slice ;o)
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Folknology wrote:So it looks as if they have separate memory maps, but communicate via the xconnect switch and I presume AHB on the ARM side, how does that appear on the Arm firmware side, what does the interface look like? From the XS1 side does it work like a Channel/Service interface?
Could I run uClinux on this thing (not that I am suggesting one should) but it sure comes with a good coms stack, can one add external RAM to achieve this?
So many questions..
regards
Al
A hint is that only 7 threads are available. I think that basically XMOS bought dice from Silicon Labs and put it on a substrate together with an XMOS die to create The gecko isn't offered in 1024KB flash, so this could mean that there is a 1024KB flash directly connected to the XMOS chip in the package. A question is whether XMOS will support the ARM part with tools and knowledge...
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They look really cool devices, only wish they came in something other than FBGA265 packages
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What sort of package would you prefer?
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It would be nice to have a package that you could hand solder (and place) for prototypes, but I don't know what the port map for this chip is so it's difficult to figure out how many pins would be required, perhaps an 80/100 pin TQFP or PQFP with 0.5mm spacing would be nice (maybe have to loose some of those GPIOs like the 32bit port).
This goes for all of the new chips with their new features and lower BOM count, it would be nice to have a selection in more approachable packages (not from a layout POV they are actually good for that, but a physical prototype POV) there are also many cases that do not require the full array of IOs.
regards
Al
This goes for all of the new chips with their new features and lower BOM count, it would be nice to have a selection in more approachable packages (not from a layout POV they are actually good for that, but a physical prototype POV) there are also many cases that do not require the full array of IOs.
regards
Al
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EFM32GG "Giant Gecko"?Bianco wrote:The gecko isn't offered in 1024KB flash
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Yay the efm32gg also has an external memory bus interface (up to 256MB), would be cool if that's exposed..
Except the XS1 is using this however (EBI), so prob not:-(
regards
Al
Except the XS1 is using this however (EBI), so prob not:-(
regards
Al