Optimizing ADC Read

[segher]

That looks a lot better :-)

The inshr/outshr insns can help with your data bus reads/writes,
get rid of the shifting/or-ing around it; it's not terribly many
cycles, but it's a useful trick to know. Similarly, maybe you
can use one 8-bit port instead of two of your 4-bit ports; and
you could put four of your 1-bit ports on one 4-bit port, but
that is a big redesign.

One more nice boost you can get is to use the sequential
mode of the ADCs: you can read all its channels without
having to write to the bus at all!

You already have the conversion (the 14 clock ticks) taking
half or so of the time, so there isn't too much to win left.

[rp181]

The hardware needs a lot of IO, so unfortunately this was the only possible way to fit everything. I did actually try the sequential mode earlier, but the benefit was only slight (most of the time is from the ADC conversion). I may try that again, though this is fast enough as-is!

I'm going to go ahead and start learning about the assembly instructions, since it seems like a useful thing to know :D

Thanks again segher!