What is the recommended practice in a multiple processor de

[Redeye]

I'm currently designing a board which will use 3 x XS1-L12A-128-TQ124 and 1 x XS1-L4A-128-TQ48. I've successfully done a similar board before but I've got a few questions that I never really got to the bottom of :

What is the recommended practice in a multiple processor design for the DEBUG_N pin? The documentation says that the pin acts as both an output and an input, but then the errata says it should be buffered in a multiple processor design (which obviously can't work if the pin is working as an input as well). In this design I'm using 3 x XS1-L12A-128-TQ124 and 1 x XS1-L4A-128-TQ48 (which has no DEBUG_N pin). So is the DEBUG_N pin useless in this design anyway?

[sethu_jangala]

Yes, the document specifies that the pin acts as both input and output and in multi-tile system it should be buffered. So, the DEBUG_N pin cannot be used for any purpose in the designs like yours.