Hi. Working on a design that is expected to use 2 x XS1 components (124 pin QFN due to the demand for the number of IO pins).
Is there a document that details how to map the XTAG-2 for full debugging of both (or more) XMOS devices ?
Believe we have most of it correct as follows:
XTAG-2_TDSRC (Host to Target) -> TDI on XMOS # 1 device (same device will also contain the boot SPI EEprom)
TDO on XMOS # 1 device will connect to TDI of XMOS # 2 device
XMOS # 2 device_TDO -> TDSNK (Target to Host) on XTAG-2
XTAG-2_TRST_N to both XMOS devices
XTAG-2_RST_N to both XMOS devices
XTAG-2_TCK to both XMOS devices
XTAG-2_TMS to both XMOS devices
XTAG-2 links to XMOS # 1 device with XMOS # 2 linked to first XMOS device as per datasheets (5 wire)
XTAG-2 UART pins to XMOS # 1 device only
How should the XTAG-2 DEBUG pin be connected for this 2 chip design for each XMOS device ? (will be expanded to more XMOS devices after this proof of concept)
How to wire up XTAG-2 for multiple XMOS ICs
-
mon2
- XCore Legend
- Posts: 1913
- Joined: Thu Jun 10, 2010 11:43 am
-
mon2
- XCore Legend
- Posts: 1913
- Joined: Thu Jun 10, 2010 11:43 am
02-16-2014
Answering most of my own questions...
Figure 9 (page 16) of XS1-L16A-128-QF124 datasheet has details on how to apply DEBUG_N for multiple devices. A pull-up is recommended when using multiple XMOS devices.
See section F which notes that for a proper drive of a LOW from the XTAG tool onto multiple XMOS devices, buffers should be applied. We missed this in our original reading so our design will be updated to reflect this suggestion.
Also, XSLICE Kit schematic can be used for guidance on how to properly buffer a daisy chained set of XMOS devices.
=======================
Although the new concern now is that the datasheet lists the DEBUG pin as being bidirectional. On the XSLICE kit there is an open drain buffer (NC74WZ07; U2) driving this pin. So with this open drain buffer in place, how does the XTAG tool or another chained XMOS device see the case where the XMOS device pulls this line LOW ? It appears that the bidirectional feature of this pin is lost if wired as shown on the XSLICE kit schematic. Any ideas ?
Answering most of my own questions...
Figure 9 (page 16) of XS1-L16A-128-QF124 datasheet has details on how to apply DEBUG_N for multiple devices. A pull-up is recommended when using multiple XMOS devices.
See section F which notes that for a proper drive of a LOW from the XTAG tool onto multiple XMOS devices, buffers should be applied. We missed this in our original reading so our design will be updated to reflect this suggestion.
Also, XSLICE Kit schematic can be used for guidance on how to properly buffer a daisy chained set of XMOS devices.
=======================
Although the new concern now is that the datasheet lists the DEBUG pin as being bidirectional. On the XSLICE kit there is an open drain buffer (NC74WZ07; U2) driving this pin. So with this open drain buffer in place, how does the XTAG tool or another chained XMOS device see the case where the XMOS device pulls this line LOW ? It appears that the bidirectional feature of this pin is lost if wired as shown on the XSLICE kit schematic. Any ideas ?