My thoughts are that I will be using the spi_slave in a dedicated thread to listen to the Rasberry Pi for incoming data (there will be a LOT of data coming in).
The spi_master(s) will be connected each to a nRF24L01+ transceiver, Hopefully connecting 3 or 4 of them. I am still trying to figure out the difference of the pin/port mappings as XC/XCORE/XMOS is all new to me. In Arduino I would have used 5 pins to control one transceiver, it seems that many of the GPIO pins on the J7 header are not 1bit so I am a little unsure about how to use the 4 bit ones as individual output pins, or if i can, more to read there I think.
So, that said, I had it all working on one nrf transciever with one Master spi module. Last night I tried refactoring to add a second spi master / nrf combo and run both masters in a par statement.
The compiler didnt like that as the SPI master code has the unsigned sclk_val; stored as a shared var. I had the masters both defined with different structs / pins but it died here:
unsigned sclk_val;
Code: Select all
void spi_master_init(spi_master_interface &spi_if, int spi_clock_div)
{
// configure ports and clock blocks
configure_clock_rate(spi_if.blk1, 100, spi_clock_div);
#if SPI_MASTER_MODE == 0
set_port_no_inv(spi_if.sclk);
configure_out_port(spi_if.sclk, spi_if.blk1, 0);
sclk_val = 0x55; //Compiler doesnt like this line much
Anyone tried this yet? Am i just missing something? It seemed to me that the sclk_val should be refactored into the spi_master_interface type?
Also, if I am using the master lib it uses two clkblks does that limit me to at most 2 master spi? since there are only XS1_CLKBLK_1-5?;