The xcore (XS1 - L, U and A series) boots in 3 stages:
1)Executes internal boot ROM (first stage bootloader) to load the second stage boot loader from SPI flash, OTP or link (if multi-chip). If booting from flash, SPI runs quite slowly (depends on mode/clock but a few of MHz typically - the divider is set to /20)
2) Executes second stage boot loader to setup links, PLL etc. and load the application (from flash or link if multi-chip). SPI runs quicker (according to boot pins/crystal and --jtag-speed setting used in xflash, which sets the divider. Run
for more)
3) Resets (on PLL configure to user application settings in .xn file) and runs application from RAM
If it is stuck before running the app, then you can use:
to find out where the processor is and what happened. The key registers to look at are PC, and SPC/ET/ED if an exception has occurred. Note these addresses are for all XS1 - L, U and A series devices as they share the same boot ROM.
If it has stopped in the ROM (first stage boot loader) it is likely to be at one of the following addresses:
Address Description
- 0xffffc070 Boot mode JTAG (waiting for program to be loaded over JTAG)
- 0xffffc0a6 Boot mode channels (waiting for boot image)
- 0xffffc300 Exception handler - see below
If the PC is in RAM (0x10000 - 0x20000) then you are in your application. If the PC is at 0xfffc300but the SPC is in RAM, the ROM has successfully loaded and jumped to the next bootloader / user application but this has raised an exception before setting up its own exception handler.
Debugging exceptions
Look at the saved PC (where was it before exception raised), ET (exception type) and ED (exception data).
- Boot from SPI. Contents of SPC, ET, ED:
- 0xffffc218, 0x5 (ET_LOAD STORE), 0x20000. SPI Image size is bigger than memory (RAM). Image size in words can be computed using 0x4000 + r5. The last word received is in r6.
- 0xffffc232, 0x5 (ET_ECALL), 0. Boot from SPI CRC failure.
- Boot from channel. Contents of SPC, ET, ED:
- 0xffffc0b8, 0x5 (ET_LOAD_STORE), 0x20000 Boot from channel image size is bigger than memory. Image size in words can be computed using 0x4000 + r2. The last word received is in r1.
- 0xffffc0a6 or 0xffffc0aa or 0xffffc0c0 or 0xffffc0c8, 0x4 (ET_ILLEGAL_RESOURCE), 0x2. Invalid boot from channel image format (unexpected or missing control token).
- 0xffffc0d4, 0x8 (ET_ECALL), 0 .Boot from channel CRC failure
0xffffc112 0x4 (ET_ILLEGAL_RESOURCE) 0x2 Race condition where bootable image is received before all links have been enabled (see bug 14028), suggests xflash hasn't used a long enough delay.