AN00170 "Using the SDRAM library"
Posted: Wed Jul 20, 2016 5:28 pm
Hi! Any news on the availability of application note AN00170 "Using the SDRAM library" mentioned in the SDRAM library user guide?
Thanks!
- Tony
Thanks!
- Tony
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The latest library (3.1.0) supports 256Mb SDRAMs OK (xCORE 200 only - so OK for XU216), so from a software perspective, that should be fine.Is there anything I should know about applying the examples to a XU216-512-TQ128 processor with one Micron MT48LC16M16A2P 256Mb SDRAM?
Code: Select all
<!-- SDRAM ports -->
<Port Location="XS1_PORT_1A" Name="PORT_SD_CAS_N"/>
<Port Location="XS1_PORT_1B" Name="PORT_SD_RAS_N"/>
<Port Location="XS1_PORT_1C" Name="PORT_SD_CLK"/>
<Port Location="XS1_PORT_1D" Name="PORT_SD_WE_N"/>
<Port Location="XS1_PORT_16A" Name="PORT_SD_ADQ_DQ_BA"/>
Yes - appolgies. This is new information from a currently unreleased (it is still being verified) document. the objective was to give you advance information to help guide you. Anyhow, I understand you are already there with hardware so let's work with what we have for now.After reading your post today, I returned to the XU216 data sheet and XS1 Port I/O Timing documents to see what I have overlooked. Searching for ‘skew’, ‘delay’, ‘RGMII’, and other related words did not return anything that would preclude selecting 16B on tile 1.
Understood! It's good that we are in dialogue so can try to asses what needs to be done now.This is just history - none of it is intended to contradict your good advice - just trying to understand how to find similar information in the future when sifting through the many pages of XMOS documentation and how to keep this project on track with the prototype board being what it is now.
Inherently, resampling to a different clock domain will introduce jitter. All XMOS I/O are resampled into the core clock domain (nominally 500MHz). This is something you can ignore for slow signals, but needs thining about for faster signals like SDRAM. The RGMII drivers are just stronger CMOS drivers with the ability to run at 2.5V on a separate I/O bank.Questions:
- Is skew the only parameter we need to be concerned about, or do the RGMII drivers also introduce jitter or affect rise/fall times?
Let me see if I can get some preliminary data..- The xCORE-200 port map spreadsheet infers that P16B8-11 (mapped to SD_AQ08-11) do not have RGMII drivers on them. Will all other signals on that port arrive behind P16B8-11? Is there any data for much skew will we encounter?
No - the stronger drive strength is fixed in the I/O pad - the tx pads have an 8mA driver instead of 4mA- Can the RGMII drivers be bypassed/disabled?
Am working on this...- In this situation, how fast do you think the SDRAM can be operated when trying to meet our testing objectives?
Not yet - we are working on an extended I/O timing document currently - I'm afraid that's weeks away.- Other than the previously mentioned documents, are there any other XMOS documents that would be helpful to review at this time?
Yes, but it's not on the near term to-do list currently.- Will AN00170 contain information about port selection, suggested component placements, and/or Gerbers?
Let me check..- Do you think we can move forward with above mentioned tests with the board as it is or are we wasting our time?
That's good. Yes, please do share how you get on.The rest of our board (supplies, power-on-reset, boot ROM, etc.) all check out OK. We'll be able to start our lib_SDRAM testing next week and can report back in mid to late August to let folks know how it's going.
You're welcome. I am aware that docs are sparse on timing, so we will focus on getting that I/O timing document out. I will raise the AN00170 issue again too.Thanks again for your expert advice and fast support!