XCore Exchange

Another question: how does the XMOS PLL develop a 500 MHz core frequency from a 24 MHz oscillator frequency?

https://www.xmos.com/download/private/x ... 1.0%29.pdf

Thank you for the link. The document indicates how to configure the system to set up clocks.

What I really wanted to know was, not how to configure the system, but how the circuit that is the PLL takes in a 24 MHz signal and produces a 500 MHz signal under the assumption that the two values must be related by an integer ratio comprising small (say, less than 100) integer values.

Is my assumption incorrect (and if so, how?), or does the PLL not actually produce a 500 MHz signal with a 24 MHz input?

-Bill