XCore Exchange

Hi.
I tried to use the Reference Design in a system which have 1024Fs MCLK.
I make the following changes in customdefines.h:
#define MCLK_441 (512*44100) /* 44.1, 88.2 etc */
#define MCLK_48 (512*48000) /* 48, 96 etc */
to
#define MCLK_441 (1024*44100) /* 44.1, 88.2 etc */
#define MCLK_48 (1024*48000) /* 48, 96 etc */

Then, I got LRCLK and BCLK with the right frequencies, with Fs=44.1/48kH, but SDATA is always 0.

With 512Fs the it works fine.
Tried at 2 boars - with XS1-L8A and also with XUF208, the same result.

1024x MCLK should be fine. On XS1 it means you have to output BCLK twice as often in the main loop but on XS2 the clock block does the MCLK to BCLK division meaning the loop underneath will not see any difference between 512x and 1024x. Saying that, we have had 1024x working even on XS1 and i have recently had 1024x working on XS2 so I can assure you the device is capable..

Does it enumerate any appear to stream OK on x1024? Do you get valid data on the USB bus?

What you have done should be enough..That's exactly what I did to get 1024x going (apart from change osc settings to get 49.152MHz)

I got the right frequency at LRCLK and BCLK, and from PC side everything is OK - player works, but there is no output at SDATA. This line is always 0.
I will check again.

If you are getting LRCLK then we know that the audio loop is looping. At the interface between the buffer (decouple.xc) and I2S (audio.xc) the rate of requesting samples does not change whether it's 1024x or 512x so it should all be the same for the rest of the system. Could you put a print in audio.xc that prints when samplesout[0] becomes non zero? Make sure you enable xscope so that printing is fast enough... Also, is the endpoint data looking valid on a USB analyser? It's going to be a case of working out where the data is getting dropped and so visibility of it at each point along the signal chain is going to be useful.

I'll check after weekend.

LRCLK was right frequency and changes when the samplerate is changed.
The same PCB with the same source code (except MCLK Freq definition) works fine with MCLK=512Fs at all PCM formats from 44.1 to 384.

Hi, it was my fault in the test signal, now there are no problem.

now there are no problem

Great! That's good news. Thanks for taking the time to close the loop.

Will be glad if somebody can help to solve the last (I hope :)) problem in this project - with DSD.
Described at another topic.