XCore Exchange

Hi,
My application is a SPDIF to i2S converter using startKIT. The problem is that SPDIF data is received faster than i2S data out. So my data buffer become full very quickly. Both SPDIF and i2S are 48K. I have measure the output frequency of i2S, it is standard 48K, but the frequency of the sample received from spdif is about 48.1K.
I don`t know why, what is the problem?

Best regards
FTS

To be clear, you are receiving SPDIF from another device, and then trying to play it out of your startKIT via I2S?

If you have:
And the source is clocked faster than the sink, then no amount of buffering will save you. Buffering can smooth out two clocks that are instantaneously different, but tick the same amount of time over the long run.

How are you getting your timing numbers? i.e. how do you know one is at 48k and the other is at 48.1k?

Hi，andrewxcav
Yes，I‘m receiving SPDIF from another device and trying to play it out of your startKIT via I2S. Just like the example AN00231: SPDIF Receive to I2S output using Asynchronous Sample Rate Conversion does.
The timing number: I flip a pin when send a sample, then use logic analyzer to measure this pin, and get it is 48K . And the same way to get the receive frequency.
The number 48.1K is not accurate in fact. To be exact，there will be one more sample been received about every second.
The SPDIF signal where I get from is my PC.

Are you getting audio output? The referenced app note should handle the clock domain issues. A full buffer is only a problem if it becomes so full that you start dropping samples and hearing problems in the playback audio.

FTS wrote: To be exact，there will be one more sample been received about every second.

Your input and output clocks are asynchronous, because operating from the different oscillators (input - from PC, output - from your clock), so there must be difference in it's frequencies.
ASRC is exactly dedicated to solve this problem, if you do not want to clock you DAC from recovered clock from SPDIF (by PLL).
Another way - to use big FIFO buffer, as in Yan's device (wee www.diyaudio.com) or JKill device (see www.altor.co ) or similar.
The idea is to have so big buffer, which can handle the clock's frecuencies difference during the song/album time duration and to reset the FIFO at pauses, or to make some correction (sample drop or repeat) to prevent the buffer over/under-flow.

But the XMOS Sample Rate Conversion (SRC) library only surport xCORE-200 multicore micro-controllers.So unfortunate.

FTS wrote:Hi,
My application is a SPDIF to i2S converter using startKIT. The problem is that SPDIF data is received faster than i2S data out. So my data buffer become full very quickly. Both SPDIF and i2S are 48K. I have measure the output frequency of i2S, it is standard 48K, but the frequency of the sample received from spdif is about 48.1K.
I don`t know why, what is the problem?

Best regards
FTS

So, your I2S is in master or slave mode ?

master mode