Audio Sync bewteen 2 tiles
Posted: Mon Nov 20, 2017 10:40 pm
Hi all,
I am experiencing a strange problem.
I have a custom board based on xCORE-200 Multichannel Audio Platform design but I added 4 I2S DAC outputs on tile 1 (audio is on tile 0 and USB on tile 1).
I took the code of sw_usb_audio_6.15.2_rc1.
I have a task on tile 1 that receives samples through a channel from the main audio I2S task : "deliver" in audio.xc and on tile 0.
In the function "deliver", I added a simple line like this :
c_send <: samplesOut[0];
to send the left sample to my custom thread located on tile 1.
My task on tile 1 looks like this for testing purpose :
while (1) {
c_receive :> sample;
p_lrclk <: 1;
p_ch1 <: 1;
p_ch2 <: 1;
p_ch3 <: 1;
p_ch4 <: 1;
}
Then I monitor my 5 signals to check the synchronicity. The signals p_lrclk show a perfect 96kHz (my sample rate) but the edges of the other signals are not in sync.
p_lrclk and p_ch1 are aligned, p_ch2 and p_ch3 are shift by 1 bit and p_ch4 by 2 bits.
If I comment the first line (c_receive :> sample;), then all the signals are in sync (at at rate > 700kHz).
To be honest, I do not understand this behaviour and I can't find any solution to that problem.
The ports are clocked like on the main audio clock on tile 1 :
set_clock_src(clk_audio_mclk2, p_mclk_in2);
set_port_clock(p_for_mclk_count, clk_audio_mclk2);
configure_out_port_no_ready(p_lrclk, clk_audio_mclk2, 0);
configure_out_port_no_ready(p_ch1, clk_audio_mclk2, 0);
configure_out_port_no_ready(p_ch2, clk_audio_mclk2, 0);
configure_out_port_no_ready(p_ch3, clk_audio_mclk2, 0);
configure_out_port_no_ready(p_ch4, clk_audio_mclk2, 0);
start_clock(clk_audio_mclk2);
They are initialized like this :
on tile[1] : buffered out port:32 p_lrclk = PORT_LRCLK2;
on tile[1] : buffered out port:32 p_ch1 = PORT_CH1;
on tile[1] : buffered out port:32 p_ch2 = PORT_CH2;
on tile[1] : buffered out port:32 p_ch3 = PORT_CH3;
on tile[1] : buffered out port:32 p_ch4 = PORT_CH4;
I tried with both a standard channel and a streaming channel to send the samples but the behaviour is the same ...
Any ideas ? Is this possible to sync several I2S outputs on two tiles using the same main audio clock ?
I would appreciate any help on this ...
Thanks
Best regards,
Nicolas
I am experiencing a strange problem.
I have a custom board based on xCORE-200 Multichannel Audio Platform design but I added 4 I2S DAC outputs on tile 1 (audio is on tile 0 and USB on tile 1).
I took the code of sw_usb_audio_6.15.2_rc1.
I have a task on tile 1 that receives samples through a channel from the main audio I2S task : "deliver" in audio.xc and on tile 0.
In the function "deliver", I added a simple line like this :
c_send <: samplesOut[0];
to send the left sample to my custom thread located on tile 1.
My task on tile 1 looks like this for testing purpose :
while (1) {
c_receive :> sample;
p_lrclk <: 1;
p_ch1 <: 1;
p_ch2 <: 1;
p_ch3 <: 1;
p_ch4 <: 1;
}
Then I monitor my 5 signals to check the synchronicity. The signals p_lrclk show a perfect 96kHz (my sample rate) but the edges of the other signals are not in sync.
p_lrclk and p_ch1 are aligned, p_ch2 and p_ch3 are shift by 1 bit and p_ch4 by 2 bits.
If I comment the first line (c_receive :> sample;), then all the signals are in sync (at at rate > 700kHz).
To be honest, I do not understand this behaviour and I can't find any solution to that problem.
The ports are clocked like on the main audio clock on tile 1 :
set_clock_src(clk_audio_mclk2, p_mclk_in2);
set_port_clock(p_for_mclk_count, clk_audio_mclk2);
configure_out_port_no_ready(p_lrclk, clk_audio_mclk2, 0);
configure_out_port_no_ready(p_ch1, clk_audio_mclk2, 0);
configure_out_port_no_ready(p_ch2, clk_audio_mclk2, 0);
configure_out_port_no_ready(p_ch3, clk_audio_mclk2, 0);
configure_out_port_no_ready(p_ch4, clk_audio_mclk2, 0);
start_clock(clk_audio_mclk2);
They are initialized like this :
on tile[1] : buffered out port:32 p_lrclk = PORT_LRCLK2;
on tile[1] : buffered out port:32 p_ch1 = PORT_CH1;
on tile[1] : buffered out port:32 p_ch2 = PORT_CH2;
on tile[1] : buffered out port:32 p_ch3 = PORT_CH3;
on tile[1] : buffered out port:32 p_ch4 = PORT_CH4;
I tried with both a standard channel and a streaming channel to send the samples but the behaviour is the same ...
Any ideas ? Is this possible to sync several I2S outputs on two tiles using the same main audio clock ?
I would appreciate any help on this ...
Thanks
Best regards,
Nicolas