XCore Exchange

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//port config:
           on tile[0] : clock clk = XS1_CLKBLK_1;
           on tile[0] : in port p_clk_in = XS1_PORT_1I;//using  external AD CLK
           on tile[0] : in port p_rd = XS1_PORT_1J;// DATA READY SIGNAL
           on tile[0] : in buffered port:32 chan_1 = XS1_PORT_1L;//DATA CHANNEL
           on tile[0] : in buffered port:32 chan_2 = XS1_PORT_1K;
           on tile[0] : in buffered port:32 chan_3 = XS1_PORT_1M;
           on tile[0] : in buffered port:32 chan_4 = XS1_PORT_1N;
           on tile[0] : in buffered port:32 chan_5 = XS1_PORT_1O;


void sample_1_3(unsigned char k)
{
                chan_1:> valdata1[k];
                clearbuf(chan_1);
                chan_2:> valdata2[k];
                clearbuf(chan_2);
                chan_3:> valdata3[k];
                clearbuf(chan_3);
}

void sample_4_5(unsigned char k)
{
                chan_4:> valdata4[k];
                clearbuf(chan_4);
                chan_5:> valdata5[k];
                clearbuf(chan_5);
}

...
          //wait for data ready signal which last about 40ns. it's not enough.

            select
            {
                case p_rd  when  pinsneq(0):> cmd:
                par{
                on tile[0]:  sample_1_3(k);
                on tile[0]:  sample_4_5(k);
                }
                k++;
                break;//
         }