XCore Exchange

The XEF216 datasheet says:

The RGMII PHY should be configured so that RX_CLK is low during reset of the
xCORE. This may be achieved by putting a pull-down resistor on the reset of the
PHY, keeping the PHY in reset until the RGMII layer on the xCORE takes the PHY
out of reset.

This is problematic for the project I'm working on, since we are actually using a switch which is brought up and configured by an external processor before the XMOS is even brought out of reset. Is there a way around this limitation without putting the switch under control of the XMOS or somehow coordinating the startup of the two?

An idea...place a 2 input open drain gate with a pull-up (10k or similar) on the output of this OD gate. This output will connect to the PHY RESET pin.

Input # 1 - to the XMOS PHY RESET pin

Input # 2 - to the external micro GPIO pin for the PHY RESET function

Only if both inputs to this gate are HIGH (ie. both micros agree that the PHY should be moved out of reset state), the output of the OD gate will remain LOW.

http://www.onsemi.com/PowerSolutions/pr ... C74VHC1G09

mon2 wrote:An idea...place a 2 input open drain gate with a pull-up (10k or similar) on the output of this OD gate. This output will connect to the PHY RESET pin.

Input # 1 - to the XMOS PHY RESET pin

Input # 2 - to the external micro GPIO pin for the PHY RESET function

Only if both inputs to this gate are HIGH (ie. both micros agree that the PHY should be moved out of reset state), the output of the OD gate will remain LOW.

http://www.onsemi.com/PowerSolutions/pr ... C74VHC1G09

The micro needs to configure the switch before the XMOS can communicate with it, allowing the XMOS to hold it in reset wouldn't help things. The two can communicate, so I can have the two coordinate so the micro brings the switch out of reset and configures it before the XMOS continues, but due to the complexity I would rather not do that if it can be avoided. Hence my question: can it be avoided?

I have a workaround involving bringing the XMOS out of reset first, having it wait while the switch is brought out of reset by the MCU, then setting the link state up on the XMOS after the switch is configured and the XMOS port brought up. However, this is still awkward, involving coordinating the initialization of the switch between the two processors, and means the XMOS can't be reset and brought back up without support on the MCU side for redoing the whole process. If there's any way to work around this, it would be preferable.

Why don't you use the XMOS reset line to control an analog mux, so when the XMOS RST_N is low the analog mux connects RX_CLK to a pull down resistor but when RST_N goes high the RX_CLK is connected to the switch.