Trouble routing a XMOS PCB

[rp181]

I am having trouble routing these last signals on an XMOS board. The idea is to have a xmos module that can plug into base boards, like the gumstix. I primarily did this so I can have parallax strips with different sensor spacings, but it could easily be used for anything else. There are 2 SMD connectors on the bottom, one for JTAG and one for an 8 bit port, plus 4 1 bit ports. If someone could take a look at it, that would be great! Feel free to play with spacing and such.

final_plan.zip

[ale500]

I see it difficult. But maybe using vias, smaller vias (dia 0.3mm) below the package could be done. I'd go with 0.15 mm tracks too, everywhere. If the size of the board were 2 or 3 mm larger it would be much easier, can you afford it ?
If you look at the board I made, I also decided to go for a two borad approach but I routed everything to the connectors, it looks simple but it went several iterations before it was ready. May be a re-route without autorouter would help. Have
fun

[ale500]

With some massaging and 0.3 mm holes and 0.2 mm tracks you can route the tracks out of that place like this

[rp181]

I got a bunch more routed, and even managed to add some single bit lines and make the board smaller. I can not figure out how to route these last two signals!

BTW, this is a general L1 XMOS module, that has two SMT connectors on the bottom, one for JTAG, and one for IO. A 8 bit port and 6 1 bit ports are broken out.
The whole board is 1.75"x.8125", two layer, minimum 6/6 traces. Most traces are 8 mill or higher, but I needed 6 mill traces for some of the traces. Does not matter from a cost standpoint, 6mill spacing was required and is in the same pricing category as 6 mill trace width.
Let me know if you can figure out how to route this.

[leon_heller]

You need to make some space for those last two tracks by enlarging the board and moving the parts further apart. I don't think you can squeeze them in as it stands. I'd make all the signal tracks 6 mil.

[ale500]

rp181: Or I missed something or that was extremely easy... :) Have fun !

Just the brd is in the zip as I did not change the schematic ;-)

Edit: You may have to add a couple more vias to finish routing GND.

[rp181]

By golly I do believe it is done! Thank you ale500! I had to move some stuff around and change sizes as you were working in metric and didn't quite pass the DRC for advanced circuits, but I kept the same concept!

Could someone look over the schematic and PCB to ensure it will work correctly? That involves checking connections, power, making sure I have all the needed signals broken out (JTAG mainly), etc...
After checking, it, whether or not you found any errors, I will send you a free populated board w/ a daughter breakout if it works without any errors (1 or 2 small easily rectified mistakes are fine) after testing the proto. Checking for useless vias and things like that will help too, I found quite a bit of vias that I put in that became useless after moving traces and such.

A note on the voltage regulator: I mapped the pins wrong on the part, and I cannot find my library file for it. Because of this, the connection to the pins on the schematic will look totally wrong, but will be correct if the physical pin layout is looked at on the brd file.

[rp181]

Oops, those board and schematic files are not consistent. Here is the fixed version.

[ale500]

The Mode pins bug me. Is it possible to boot via JTAG when the mode pins (2&3) are not 0 ? In the reference circuit by XMOS they tie these pins to T_NRST so when you reset the device via JTAG the mode pins say boot from JTAG. (I did this in my board too). What are you thoughts about it ?.

Btw: the board can be made "prettier" moving a couple of tracks to fill more area with GND... I'm a big fan of 45° angles, and thus many tracks can be massaged to fit "better" :)

[rp181]

Which reference design is this in? I had put a solder jumper to choose between flash boot and jtag boot since I could not find anything on having it automatic. I will change it to be automatic then!

EDIT: I don't know what changes you have made, but there is a via next to the crystal that is needed, there is no connection to the top layer. That can be unrouted, and will fill more GND.

EDIT2: Here are the changes I made as you said to increase ground plane coverage and removed the useless via, and found some trace width mismatches. Here it is with all the changes minus the MODE pins.