One other possibility is to multiplex a single 1 bit port onto both QSPI chip's SI and use the remaining 1bit port to control an output enable on that port (via 2 hi-z buffers), that way the 4/8bit port can be input without needing the switch direction around.
I think you missed another 4/8 somewhere ? QuadSPI flips by opcode, so needs to send the Address info right after that 1 byte opcode, as Quad/Quad_DDR, so you need full DDR half-duplex port operation.
(see my note about a 64 bit remapped opcode, to avoid any HW gymnastics at the opcode/address boundary)
Sure, additional silicon and pins could be used, but that is an admission of defeat... ;)
I can however see fish-hooks in the turn-around from send-address to receive data, but there are also latency bits in the Spansion Memory, and as long as the turn-around was always a fixed clock count, you can correct for it. Jitter would be the killer here.
I've thought about this issue I mentioned above, and think it can be checked by running a single additional receive channel, on the CLK-as-Data line.
Yes, it is more house-keeping, but it could be use to prove there really is a thread-immune system.
This would record the time the DDR clock really
spends paused (because the internal sampling 2x clock does NOT pause, this time matters )
With no pauses, this will simply always read the 55H or AAH on the SPIqCLK line. During the turn-around time between address send and data in, this will show exactly how many 2x samples it took, and how much needs to be discarded to properly sync to real data.
In flow terms, you wait for Address block to send, then disable qDIO so make Rx only, then flush/restart receive and send receive clock.
The bit that ideally needs to be atomic is the "flush/restart receive and send receive clock", as you want a known and fixed delay here.