Which Program Flow?

[rp181]

Here is the breakdown.

Core 1 of the L2 device is entirely devoted to USB.
On core 0:
-4 ADC's . I am liking the AD9054A right now. Each ADC has a 8 bit parallel port for data, so that cuts all 8b ports available out. In addition, each ADC needs an ENCODE signal to trigger when to sample, so that takes 4 more 1 bit ports.
-On each ADC, I need a 16:2 multiplexer. At this point, I only have 4 1 bit ports available, so I am hoping I can use a counter on each of those 1 bit ports to drive a 16:1 multiplexer that takes a 4 bit parallel input.

[Folknology]

Ok I a bit confused using the AD9054A, you would only need 2 ADCs feeding the 4 * 8bit ports no?

regards
Al

[Folknology]

With 2 * AD9054A and analogue multiplexers in front of them along with an external oscilator/clock master and a binary counter you could do it all.

You then tap the counters first 4 stages to drive the 2 analogue multiplexers, then the next stage is tapped for the sample clock ( encode) for both ADCs, the 6th tap is then used (sample/2) to drive the 4 1bit lines this acts as the data transfer trigger to each thread on each 8 bit port (4 separate threads, 1 for each port).

Basically the clock oscillator determines how fast it all happens and is selectable, the L2 could handle it (sampling at 100Mhz)up to about 3.2Ghz master clock, but not sure you'd get the ADC, multiplexers or counters working at that rate!!

Basically this scheme will be limited by multiplexer switching freq and ADC settling time in dual channel continuous mode

regards
Al

[Folknology]

Actually the sample tap is at clk frequency and the 4 * 1 bit taps are from the first stage, multiplexers from higher stages.

Something like a M74HC4060 only faster (~200Mhz) would be handy

regards
Al

[Folknology]

You could use something like NB3N3002 and 25Mhz crystal as your master and then perhaps just a counter divider made up of perhaps 74HC393 and a pair of D-types to generate all the timings.

*Update in fact you might be able to get all the timings using NB3N3002, 25Mhz crystal and 74VHC175M (quad D flip flop)
*Update 2 actually you could loose the crystal and use the SPI clock into the NB3N3002 instead.

regards
Al

[rp181]

The ADC is actually single channel, and I will only be using one of the 8 bit ports from each. The purpose of the two 8 bit ports is to read the data at high speed, when the micro controller can not handle that speed on a single port. So there will be 4 ADC's for 4 8 bit ports.

I will take a look at everything else you said!

[Folknology]

Right I get you.

The rest still applies however, just the Mux and ADCs operate at half the freq obviously.

However that ADC is a 200Mhz device twice as fast as XS1 can handle hence my 4 down to 2 ADC assumption, I should have looked deeper at the data sheet. It might still be possible if the ADC settling time is fast to only use 2, but the mux would need to run at twice the speed of course.

With 4ADCs running at 100Mhz you could also loose the NB3N300 by providing a clock directly from the L2.

Ask away if you have any Qs

regards
Al

[Folknology]

Tip: Generally your probably better off using core 1 for the USB, leaves more pins available for I/O that way.

regards
Al

[rp181]

I decided I am going to use a L2 device, and a L1 for the USB. This way I can scale it easily with much more IO. Each L2 core will have 2 ADC's and 2 16:1 Mux. This takes 3 8 bit ports, and leaves plenty of 1 bit for control.