Which Program Flow?

Technical questions regarding the XTC tools and programming with XMOS.
User avatar
Folknology
XCore Legend
Posts: 1274
Joined: Thu Dec 10, 2009 10:20 pm

Post by Folknology »

Oops, thanks for that Segher, i just learnt something!

regards
Al


User avatar
segher
XCore Expert
Posts: 844
Joined: Sun Jul 11, 2010 1:31 am

Post by segher »

Interactive_Matter wrote:Is a function call that bad?
Even if I say it is 'static inline'?
Or is a makro the only real guarantee for inlining?
Function calls aren't bad. Calling a function (in the generated machine code)
many many times per second _is_ bad (the call, return, and register save
and restore instructions all take time; the parameters have to be in specific
registers, which means the caller has to move them there, which takes some
insns or at the very least prevents the optimiser from doing more efficient
register assignments); and it prevents the optimisers from melding the insns
in the called function with insns in the caller, or even optimising some of it
completely away.

If you declare a function as "static", it is more likely to be inlined; if you declare
it as "static inline", even more likely (it is no guarantee though!)

Macros are no guarantee the generated code will not be a function call, either
(but it is *really* unlikely in that case). Macros have no advantage over inline
functions, in general (and quite severe disadvantages).
User avatar
Interactive_Matter
XCore Addict
Posts: 216
Joined: Wed Feb 10, 2010 10:26 am

Post by Interactive_Matter »

segher wrote:
Interactive_Matter wrote:Is a function call that bad?
Even if I say it is 'static inline'?
Or is a makro the only real guarantee for inlining?
Function calls aren't bad. Calling a function (in the generated machine code)
many many times per second _is_ bad (the call, return, and register save
and restore instructions all take time; the parameters have to be in specific
registers, which means the caller has to move them there, which takes some
insns or at the very least prevents the optimiser from doing more efficient
register assignments); and it prevents the optimisers from melding the insns
in the called function with insns in the caller, or even optimising some of it
completely away.

If you declare a function as "static", it is more likely to be inlined; if you declare
it as "static inline", even more likely (it is no guarantee though!)

Macros are no guarantee the generated code will not be a function call, either
(but it is *really* unlikely in that case). Macros have no advantage over inline
functions, in general (and quite severe disadvantages).
Thanks since that is what I wanted to hear. Functions are very usefule for code reuse and structure - so It is good to know how to reduce the impact on code performance.
User avatar
rp181
Respected Member
Posts: 395
Joined: Tue May 18, 2010 12:25 am

Post by rp181 »

New problem (hardware)

The IOs I have available are 4 8-bit ports and 4 1 bit ports. The 8 bits ports are used by the ADCs, which have a parallel interface.

I need to figure out if i can use 4 1 bit ports to multiplex all of the ADCs. Most multiplexers take a 4 bit parallel interface - the problem with that is I would have to go back to using a single ADC thread, as different threads can't control it. Any ideas?
User avatar
Folknology
XCore Legend
Posts: 1274
Joined: Thu Dec 10, 2009 10:20 pm

Post by Folknology »

How many and which ADCs are you intending using?

regards
Al
User avatar
Folknology
XCore Legend
Posts: 1274
Joined: Thu Dec 10, 2009 10:20 pm

Post by Folknology »

Here is an idea

Each 1 bit port can drive a binary counter, that in turn drives the multiplexer for that ADC (Quadrant), then you just have to clock that 1 bit port through the pixels sampling as you go on the 8 bit port. (You could get away with a single counter in fact and synchronise all quadrant multiplexers, driven by a single 1 bit clock)

Update* In fact can't you just use the 4 1bit to drive the multiplexers in parallel like the counter above, you might need an extra 1bit clock pin?

(I am assuming that the ADC can't multiplex itself directly, what are the ADCs you are using)

PS what is the max sampling rate you need for the ADCs?

Regards
Al
User avatar
rp181
Respected Member
Posts: 395
Joined: Tue May 18, 2010 12:25 am

Post by rp181 »

The number is 4 ADCs, which is fairly concrete. I don't know which specific ADC, but it will be a single channel 8 bit ADC, no multiplexer built in. As for sampling rate, above 20 million, below 80 million, most likely 40ish. 20 million will allow for 100 kHz, but I want to be able to go higher. 32 Million will give 500kHz.

I am going to see if 2 L1s would have more IO than a L2.
User avatar
Folknology
XCore Legend
Posts: 1274
Joined: Thu Dec 10, 2009 10:20 pm

Post by Folknology »

I am going to see if 2 L1s would have more IO than a L2.
Only if they were L1-128s, and even then all you are getting is part of two 32 bit ports as you would probably want to link their Xlink B&C together as the L2 does internally. This route sounds very inefficient and will greatly increase your BOM and CB complexity for very little benefit. Adding a simple counter would be much simple and cost about 20c.

regards
Al
User avatar
rp181
Respected Member
Posts: 395
Joined: Tue May 18, 2010 12:25 am

Post by rp181 »

Oh, ok.
Update* In fact can't you just use the 4 1bit to drive the multiplexers in parallel like the counter above, you might need an extra 1bit clock pin?
So where would I get that extra clock? Maybe parallel with the ADC clock (which is probably going to be 100 MHz)? I will need to look more into counters.
User avatar
Folknology
XCore Legend
Posts: 1274
Joined: Thu Dec 10, 2009 10:20 pm

Post by Folknology »

Or you could reuse the SPI clock that you use for your flash, just ramp it up after booting.

I don't know what ports you are using so its difficult to guess, can your provide a breakdown of port usage perhaps?

regards
Al