Hi all,
Little help needed.
I am trying to use port counter.
In XMOS example count += 3. but in my tests code stop working if number less then 8 is used. Can somebody explain why?
Here is code:
#include<platform.h>
on stdcore[1]: out port toggle = XS1_PORT_1A;
int count;
void gen()
{
toggle <: 0 @ count ; // timestamped output
do {
{
count += 10;
toggle@count <: 1; // timed output
count += 10;
toggle@count <: 0; // timed output
}
} while (1);
}
int main()
{
par
{
on stdcore[1]:gen();
}
}
I am using XDE 12.2 and XC-1A
thanks
cicga
Port counter speed
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You need to have time to perform the instructions as well.
Take a look at the instructions used (using debug and or disassembly)
from
toggle <: 0 @ count ;
to
toggle@count <: 1; // timed output
their is maybe 5-7 instructions ?
If you miss the time on the port you will need to wait until the counter has wrapped around.
If you decrease the frequency of the counter for an example 1:256, it probably will work.
On the other-hand, if you need to create a signal with a frequency >> 1 MHz consider to use serialized 1-bit port instead.
Take a look at the instructions used (using debug and or disassembly)
from
toggle <: 0 @ count ;
to
toggle@count <: 1; // timed output
their is maybe 5-7 instructions ?
If you miss the time on the port you will need to wait until the counter has wrapped around.
If you decrease the frequency of the counter for an example 1:256, it probably will work.
On the other-hand, if you need to create a signal with a frequency >> 1 MHz consider to use serialized 1-bit port instead.
Code: Select all
//init code with a 32 bit buffered port
while(1)
toggle<:0b10101010101010101010101010101010;
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- Active Member
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Hi lilltroll,
unfortunatly sounds right:(
what i need is fine adjustment of pulse width depends on external conditions. Pulse width should be from 50ns up to 100 ns. and serialization cannot be fine adjusted because of clock devision settings is very rough.
thanks
cicga
unfortunatly sounds right:(
what i need is fine adjustment of pulse width depends on external conditions. Pulse width should be from 50ns up to 100 ns. and serialization cannot be fine adjusted because of clock devision settings is very rough.
thanks
cicga
-
- XCore Expert
- Posts: 754
- Joined: Thu Dec 10, 2009 6:56 pm
Did you build the code in release mode (-O2)?
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- Active Member
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- Joined: Tue Oct 11, 2011 4:48 pm
lilltroll,
you kind of right that from
"
toggle <: 0 @ count ;
to
toggle@count <: 1; // timed output
their is maybe 5-7 instructions ?"
but inside loop the is no any instructons between
count+=5;
toggle@count <: 1
so how here can be delay?
bianco:
yes I build the code release mode(default settings). I am not sure about -O2 level. I doam not sure how to check it under 12.2.0 releaseXDE
thanks
cicga
you kind of right that from
"
toggle <: 0 @ count ;
to
toggle@count <: 1; // timed output
their is maybe 5-7 instructions ?"
but inside loop the is no any instructons between
count+=5;
toggle@count <: 1
so how here can be delay?
bianco:
yes I build the code release mode(default settings). I am not sure about -O2 level. I doam not sure how to check it under 12.2.0 releaseXDE
thanks
cicga