Problem at first load with JTAG

[norman]

Hello !

so i've got an issue with my new board. Little historic : i've bought an XR-AVB-LC-BRD, works fine for my application, draw and make a first prototype and works fine but needs corrections in some parts. So i make a second prototype and now can't load the first program.

Xtime composer says that the "XMOS XTAG2 is connected to none".

the problem is quite similar with this one : http://www.xcore.com/forum/viewtopic.ph ... hilit=jtag.

I've looked at the supplies and the boot sequencing, nothing seems wrong. The clock looks fine and i can see some activity after the boot on the SPI bus in order to load the flash program that - of course - do not exist.

i've tried to compare the signals RST, TRST, TMS, TCK, TDO between the XR-AVB-LC-BRD and the new one, i saw some difference but can't explain them :
On the XR-AVB... :
TRST and RST stay at VDD all the time, activities on TMS, TDO, TCK, ok fine.

On the new :
TRST and RST have a pulse VDD-GND and no activity on TMS TDO. TCK have some activity but stop quickly.

I don't understand the difference because the schematics are very very close. Does anybody have an idea, something to test or to explain before starting from zero with the schematic ?

thanks a lot !

[larry]

No activity on TMS would indicate a problem. Any JTAG command such as doing "xrun -l" should generate TMS activity. I would look into that to see if it could be a hardware issue. Swapped pins? Contention?

[norman]

thank you, indeed, i've got some activity on TMS, my scope wasn't on a good time scale. I'm looking at TRST and RST drive by the Xtag. for the moment, i don't understand the difference of behavior between the XR-AVB and my board. I will post the schematic later, if i do not find anything else.

[norman]

after searching for hours, i'm confused... I've attached the schematic for the booting part.
The 1V is 1 second delayed from the 3.3V
if someone can have a look, it might be so helpful !

I've read in some topics that TRST_N should be tied to RST_N and so be disconnect from MODE2 MODE3 as it is on the XR_AVB_BRD ?

Thanks for the help !

[Folknology]

..
The 1V is 1 second delayed from the 3.3V
..

This sounds a bit long to me, here is what an L1 series datasheet says :

The device has the following power supply pins:
· VDD pins for the xCORE Tile
· VDDIO pins for the I/O lines
· PLL_AVDD pins for the PLL
Several pins of each type are provided to minimize the effect of inductance within
the package, all of which must be connected. The power supplies must be brought
up monotonically and input voltages must not exceed specification at any time.
The VDD supply must ramp from 0 V to its final value within 10 ms to ensure
correct startup.
The VDDIO supply must ramp to its final value before VDD reaches 0.4 V.

The PLL_AVDD supply should be separated from the other noisier supplies on
the board. The PLL requires a very clean power supply, and a low pass filter (for
example, a 4.7 Ω resistor and 100 nF multi-layer ceramic capacitor) is recommended
on this pin.
The following ground pins are provided:
· GND for all supplies
All ground pins must be connected directly to the board ground.
The VDD and VDDIO supplies should be decoupled close to the chip by several
100 nF low inductance multi-layer ceramic capacitors between the supplies and
GND (for example, 4x100nF 0402 low inductance MLCCs per supply rail). The
ground side of the decoupling capacitors should have as short a path back to the
GND pins as possible. A bulk decoupling capacitor of at least 10 uF should be
placed on each of these supplies.
RST_N is an active-low asynchronous-assertion global reset signal. Following a
reset, the PLL re-establishes lock after which the device boots up according to the
boot mode . RST_N and must be asserted low during and after power up
for 100 ns.

[mon2]

As Al noted, the 1V0 enable is being delayed too long apart from the 3V3 power rail. Once the voltage threshold of 3V0 (3.0 volts) is reached for the monitored 3V3 (3.3 volt) rail, the TPS3808 supervisor starts its timer. The time delay function is related to the value of the capacitor being placed on pin 4 (CT). Your schematic is listing a value of 0.1 uf which will lead to approximately a 1 second delay before the 1V0 (1.0 volt) regulator is enabled (see attached graph from the TI datasheet). This 1 second delay is too long.

Consider to remove the 0.1 uf capacitors on pin 4 of both of the TPS3808 devices. By removing C269 an C273, the time delay will change to 20 ms which should be ample for this device.

Also, you may be able to save some bill of material costs by using a different vendor for this fairly common part. Be sure to review the footprint and delay value details if using a cross.

Good luck !

Update
=====

The capacitors shown in the schematic are rated at 50 volts and such high voltage support is not necessary. You will be fine to consider even 6.3 volts or 10 volts for this project.

Respectively, the schematic is showing the use of 1% tolerance for the resistors. Such accuracy is not necessary for this portion of the design - consider 5%.

Both of these changes will assist you to lower you bill of material costs without impacting the operation of this design.

Be sure to have a quick read the following article on capacitors vs. voltage vs. size:

https://www.maximintegrated.com/en/app- ... vp/id/5527

[norman]

Hello
thanks for the help. Unfortunately, it's not working for the moment. I've reduced the delay between the 3V3 (VDDIO) and 1V (VDD) to 500ms instead of 1s (I also tried with 100ms). VDD rise in less than 1ms.

I also tried to remove the capacitors of the TSP3808, it start faster but still no connection with the xtag2.

As i compare delay between supplies and RST / TRST, i've got almost the same result between the XR-AVB-LC-BRD (which works) and mine, around 500ms.

I will looking at TDO TDI... to try to found something

[mon2]

Remove power to the board and then perform a continuity test between:

XTAG add-on board Pin 1 and confirm that you are truly mated with Pin 1 of your XSYS connector and continue to confirm the same for the balance of these pins. This is vital as the XTAG pins may be mismatched which is very easy to do.

[mon2]

C185 on the PLL_AVDD (pin A38) is 1uf in your schematic. The recommended value is 100nf = 0.1uf. The bulk cap is nice to have but technically will filter different frequencies.

http://www.justradios.com/uFnFpF.html

[mon2]

This ride is not over yet :) Please confirm the status of the following power pins as they are not all listed in the posted schematic. Are all of these circled pins connected ?

The center metal pad must also be connected to ground.