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PostPosted: Sat Dec 12, 2009 8:42 am 
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For my 1-wire toolkit implementation (see projects), I need a simple binary oscilloscope with a resolution of about 3 microseconds. I'm away from my normal office and have nothing to hand, so I'm considering making a software scope running on an XC-2. I'll use as a basis the XC-2 firmware web-server, with an extension that reads a buffer from a thread that samples a port for a certain duration at at a certain frequency. I think this would be generally useful, so I'll probably open another project, to see what interest there is.

Anyway.... As I work through the web server code, which is pretty complex, IMHO, I would love to have a circles-and-arcs style of diagram, with channels labelled, and possibly with protocol annotations. If those circles could be drawn within a representation of their allocated cores, and annotated with module names, so much the better. If this were implemented in SVG, there could be active links to more detailed diagrams, and perhaps to source code. The results could also be rendered to PDF for project documentation.

Has anyone done anything like this? This would be a great addition to the toolkit, and is about the right size for a student project.

If I hear of nothing in the next few days, then take this as a project proposal, and I'll make a project outline.


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PostPosted: Sat Dec 12, 2009 10:50 am 
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That sounds like a nice project.

Meaby you could sample at 100Mhz using the serial features of a 1bit port. So then you would have it sample at 100Mhz and assemble those 1 bits in to 32bit integers.that way your code only needs to complete a loop in 32 instructions to take away the integer in to a buffer.

Also the XC-2 has a 4 core chip on there so you could make like a 24 channel logic analyzer with it.3 cores doing the capture and 1 core handling the web server. Also each core has 64KB of ram so you could have like 480K samples if you only use 1 channel (That would mean quite a lot of captured data)

Oh and the scope part can be run inside the simulator to find out how fast can it be made to go.


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PostPosted: Sat Dec 12, 2009 10:58 am 
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Thanks Berni, all good suggestions..

I'll get things to the point that I have a singhe channel, then make the code available. We can look at it together.

I have not found out how to get the free RAM on a core, yet, but when I build the web server firmware, I get the (below) values from the constraints checks. As you can see, there is quite a lot going on in the G4 already, although some of the threads are blinky lights.

My goal is to clear out one core, for my use for 1-wire, and get the web server into the other three (or less).

Best wishes,

--r.


Code:
Constraint check for node 0, core 0:
  Stack available:   0000d93c,   used: 00000168 .  OKAY
  Threads available:        8,   used:        4 .  OKAY
  Timers available:        10,   used:        4 .  OKAY
  Chanends available:      32,   used:       14 .  OKAY
    Constraints checks PASSED.
Constraint check for node 0, core 1:
  Stack available:   000018bc,   used: 00000234 .  OKAY
  Threads available:        8,   used:        2 .  OKAY
  Timers available:        10,   used:        1 .  OKAY
  Chanends available:      32,   used:        6 .  OKAY
    Constraints checks PASSED.
Constraint check for node 0, core 2:
  Stack available:   00001e48,   used: 00000528 .  OKAY
  Threads available:        8,   used:        7 .  OKAY
  Timers available:        10,   used:        4 .  OKAY
  Chanends available:      32,   used:       15 .  OKAY
    Constraints checks PASSED.
Constraint check for node 0, core 3:
  Stack available:   0000d4a8,   used: 00000698 .  OKAY
  Threads available:        8,   used:        2 .  OKAY
  Timers available:        10,   used:        1 .  OKAY
  Chanends available:      32,   used:        5 .  OKAY
    Constraints checks PASSED.


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PostPosted: Sat Dec 12, 2009 11:01 am 
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But I should bring the thread back to the topic of analysis/doc tools....

Quote:
Anyway.... As I work through the web server code, which is pretty complex, IMHO, I would love to have a circles-and-arcs style of diagram, with channels labelled, and possibly with protocol annotations. If those circles could be drawn within a representation of their allocated cores, and annotated with module names, so much the better. If this were implemented in SVG, there could be active links to more detailed diagrams, and perhaps to source code. The results could also be rendered to PDF for project documentation.

Has anyone done anything like this? This would be a great addition to the toolkit, and is about the right size for a student project.

If I hear of nothing in the next few days, then take this as a project proposal, and I'll make a project outline.


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