synchronized clocks

[sleepless]

I've searched headers, pdfs and forums and haven't found the answer to what is possibly a silly question.

I need to clock out synchronous data but the input side reads on the rising and falling edge of the clock. My simple solution (since I believe this is not natively possible in xmos chip) was to overclock the data:


clock clk1Mhz = XS1_CLKBLK_1;
clock clk2Mhz = XS1_CLKBLK_2;
...
configure_clock_rate(clk1Mhz,50,50);
configure_clock_rate(clk2Mhz,50,25);
configure_port_clock_output ( CLCK , clk1Mhz );
start_clock(clk1Mhz);
start_clock(clk2Mhz);

... output data on ports clocked with clk2Mhz

There appears to be about a 30ns delay between the rising edge of the two clocks. From my readings it seems they should be closer in time since they are sourced from the same reference clock . At 1Mhz 30ns is not much, but at 10 it starts to impinge on the timing of setup and hold times. Is there a way to better synchronize the clocks or measure the delay so I can appropriately delay one of the clocks ?

TIA

[Folknology]

I need to clock out synchronous data but the input side reads on the rising and falling edge of the clock. My simple solution (since I believe this is not natively possible in xmos chip) was to overclock the data:

Can you add an inverter to the input and feed it to a second input pin, then you can use both inputs to trigger on the same rising edges (inverted one will be actually the falling edge of course).

*Actually you don't even need a gate an npn with built in bias resistors could do the job.

regards
Al

[sleepless]

sorry, my terminology was a little confusing. the xmos chip is the source, an external device is the sink. I am triggering clocked, serialized data out on a pin which I believe can only trigger on one edge.

out buffered port:8 SEROUT = XS1_PORT_1A;

thanks

[Folknology]

Ooops my bad, didn't read it properly..

Have a look in the XS1.h there are some useful functions in there like these :

Code: Select all

void set_clock_rise_delay(clock clk, unsigned n):
void set_clock_fall_delay(clock clk, unsigned n);

They might be able to help straighten out the phase. there are all sorts of goodies hidden in that header file ;-)

regards
Al

[sleepless]

I did see those functions and use them to attempt to align the rising edge of my 2x clock 90 deg out of phase with the clock out, however the inherent delay is a problem. It depends on which clock is started first and I don't know if it is constant in all situations so I do not want to rely on it.

thanks

[Folknology]

Well the clock starting should be deterministic (assuming other threads aren't doing anything untoward). I am not sure what start_clock(clk) actually turns into in terms of instructions (you could try dissembling), you could code it in ASM and perhaps reduce the delay and make it more guaranteed?

regards
Al

[richard]

One thing you could do is output the 1MHz clock as a data, i.e.

Code: Select all

clock clk2Mhz = XS1_CLKBLK_1;
buffered out port:32 CLCK;
...
configure_clock_rate(clk2Mhz,50,25);
configure_out_port ( CLCK , clk2Mhz, 0 );
start_clock(clk2Mhz);
// Output clock edges
CLCK <: 0x55555555;
...
output 32 data values here
...
// Output next clock edges
CLCK <: 0x55555555;
...

This uses 1 less clock block and data will be aligned to clock edges. The downside is you need to continuously perform outputs to drive the clock signal.

[sleepless]

didn't think of that one. Not really worried about exhausting clock blocks, but that might actually not be too painful, and certainly less painful than my current alternatives.

thanks for the tip

[Folknology]

Richard its a shame that the buffered output port shift registers don't have an automatic recycling/reloading feature..

[larry]

Richard its a shame that the buffered output port shift registers don't have an automatic recycling/reloading feature..

This would indeed be nice to have. Another use is I2S master.