First of all, the SU2 dual-core device will likely be a BGA140 package with 6 analog inputs.
That should be a neat device, a multi-core in a BGA :-)
Furthermore you don't need a decent reset signal anymore, there is an internal reset generator.
This will work when you use the integrated regulators, I don't know about external supplies yet, but there won't be many using that anyway (besides me :p).
You still need to bring up VddIO before Vdd I suppose?
If anyone has paid attention, the TRST_N signal is not routed out anymore.
This signal is internally generated. JTAG can be reset with a sequence on the TMS and clock line, which is already been done for a while when you use the XTAG2.
Yeah I noticed. There is also a new IDCODE, and an extra device in the chain.
TRST is not the same as sending five ones on TMS. For one thing, TRST is
asynchronous, while the TMS thing is synchronous to the JTAG clock (and
requires that clock!) On the G4 you really need TRST, but on the L1
everything JTAG seems to be fixed (yay!), so we can do without.