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PostPosted: Thu Mar 22, 2012 12:26 pm 
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What is the intended application for the on-chip ADC? Being only 12-bits, it isn't suitable for high-quality audio, which is obviously where the device will mainly be used.


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PostPosted: Thu Mar 22, 2012 12:38 pm 
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Analog sensors and perhaps battery voltage monitoring?
While very suitable for audio, its still a general purpose device.


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PostPosted: Thu Mar 22, 2012 8:47 pm 
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When will you guys be releasing the schematics for the Audio board based on the SU1? Or the example schematic?


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PostPosted: Fri Mar 23, 2012 12:26 am 
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leon_heller wrote:
What is the intended application for the on-chip ADC? Being only 12-bits, it isn't suitable for high-quality audio, which is obviously where the device will mainly be used.


As far as i understand its to make it more useful as a microcontroler as those almost always have 10 or 12bit ADCs, Audio ADCs are usually kept in separate chips away from that noisy CPU in order to make some actual use out of there bit depth.

But i don't see this as being a very good MCU because it lacks I/O. You often want to connect a heap of stuff to MCUs. The package might not be the best for MCUs too since they almost never come in BGAs for obvious reasons.

But for the audio solutions that are so very popular it fits in great.It has all the vital stuff you need inside it minus the audio codec, but that is usually kept external.


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PostPosted: Fri Mar 23, 2012 11:02 am 
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Inside this library (not sure if the other parts have been tried by the way) is my recently created XS1-SU1 part for Eagle. Clearly this has not been checked or tried and comes with no guarantees please take a look however and let me know if you find any errors or have any feedback etc..

Attachment:
File comment: Xmos Eagle library including XS1-SU1
xmos-lbr.zip [7.57 KiB]
Downloaded 42 times


regards
Al


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PostPosted: Fri Mar 23, 2012 2:22 pm 
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Hello XCORE!,
Its been well over a year since I last posted to these forums.
I have been in stealth mode for quite a time now.
This chip, XS1-SU1 has a lot of potential, to me for many applications.
The ADC shall be effective in sniffing with the tightest possible latencies.
And sure the ENOB resolution would not warrant using it for all audio solutions,
I am sure it was never meant to be, It would take a lot more silicon and heat to
achieve higher ENOBs. Also as spoken early on this thread someone pointed to
the fact of isolation of ADC's in audio use. For audio boards, say,,, for live prossess
modules, the ADC within the SU1 would be superb for control voltage applications.
making dynamic control for audio very simple, affordable, and tightly tweaked.
And of coarse it applies across the whole electronic industries, its a supper PID, PLLC etc...
This new XS-1S line, shall adapt well for systems chips in massive XMOS hierarchies.
The AS1-SU1,,, I agree! has very good marketing potential.
Waiting with baited breath for the new release...
Shawn 8-)


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PostPosted: Mon Mar 26, 2012 12:49 pm 
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Some info that I found on the net that hasn't been publicly released by XMOS yet, but leaked from a distributor.

First of all, the SU2 dual-core device will likely be a BGA140 package with 6 analog inputs.

Attachment:
File comment: SU2 Information
SU2.png [234.11 KiB]
Not downloaded yet


Second, there will be another SU1 development board, which is different from the DJ kit on the website right now. There is a main board containing the microprocessor and power etcetera and an attachable audio interfacing board with 4 x input, 4 x output, MIDI in & out and a bunch of LEDs.

Attachment:
File comment: SU1 USB 2.0 Development board
SU1_dev.png [171.88 KiB]
Not downloaded yet


Also the ADCs are on a separate node that is fully routable in the system, so with multi-chip setups you can access the ADCs of another chip directly through a channel.

Furthermore you don't need a decent reset signal anymore, there is an internal reset generator.
This will work when you use the integrated regulators, I don't know about external supplies yet, but there won't be many using that anyway (besides me :p).

If anyone has paid attention, the TRST_N signal is not routed out anymore.
This signal is internally generated. JTAG can be reset with a sequence on the TMS and clock line, which is already been done for a while when you use the XTAG2.


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PostPosted: Mon Mar 26, 2012 4:58 pm 
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Hey nice find Bianco, maybe we should concentrate on places other than the forum for new info ;-)

regards
Al


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PostPosted: Tue Mar 27, 2012 9:17 am 
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Bianco wrote:
First of all, the SU2 dual-core device will likely be a BGA140 package with 6 analog inputs.

That should be a neat device, a multi-core in a BGA :-)

Quote:
Furthermore you don't need a decent reset signal anymore, there is an internal reset generator.
This will work when you use the integrated regulators, I don't know about external supplies yet, but there won't be many using that anyway (besides me :p).

You still need to bring up VddIO before Vdd I suppose?

Quote:
If anyone has paid attention, the TRST_N signal is not routed out anymore.
This signal is internally generated. JTAG can be reset with a sequence on the TMS and clock line, which is already been done for a while when you use the XTAG2.

Yeah I noticed. There is also a new IDCODE, and an extra device in the chain.

TRST is not the same as sending five ones on TMS. For one thing, TRST is
asynchronous, while the TMS thing is synchronous to the JTAG clock (and
requires that clock!) On the G4 you really need TRST, but on the L1
everything JTAG seems to be fixed (yay!), so we can do without.


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PostPosted: Tue Mar 27, 2012 12:32 pm 
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segher wrote:

Bianco wrote:
Furthermore you don't need a decent reset signal anymore, there is an internal reset generator.
This will work when you use the integrated regulators, I don't know about external supplies yet, but there won't be many using that anyway (besides me :p).

You still need to bring up VddIO before Vdd I suppose?



When you use both integrated regulators (And thus only supply VBUS to PVIN and 3V3 to VDDIO), power supply sequencing is implemented.
I suppose that the POR will monitor the 3V3.


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