X
RSS YouTube LinkedIn Twitter XCore IRC

Search




Post new topic Reply to topic   [ 4 posts ] 
Author Message
PostPosted: Mon Feb 27, 2012 5:15 pm 
Joined: Mon Feb 06, 2012 11:42 pm
Posts: 29
Hello guys,
I've been going through a lot of the datasheets for various boards such as the L1 USB Audio board and the XK-1A and had some questions that I cant answer without some more help.

1. On PAGE 2 of the L1 USB Audio Schematic (https://www.xmos.com/download/public/USB-Audio-2.0-Ref-Design-XS1-L1-Schematics(1.2).pdf), I noticed that the USB receptacle has 6 pins and I'm confused as to what pins 5 and 6 are. Also the resistor that's connected to both of these pins doesn't have a value and only marked as 'DNP'. Could someone explain this?

2. I noticed that on the XK-1A shematic (PAGE 13/15 in https://www.xmos.com/download/public/XK ... Manual(1.0).pdf) there isn't a delay on the RST_N pin like I would expect from the minimum requirements so that VDDIO and VDD could come up before RST_N. How is this taken care of?

3. Also on the same schematic, I have no idea why buffers are used in this way. Could someone explain why they are used and why they are used on on the 'TRST_N', 'TMS', 'TCK', and 'RST_N' pins?

4. I've noticed in a lot of schematics tie the MODE(2:3) pins together (XK-1A schematic). However, this creates a problem if you wanted the devices to boot via XLink B. Could someone explain the use of TRST_N on these two pins, does it just idle low when plugged into the board? I'm guessing that the pins are pulled up so that when the JTAG isnt' connected then the device boots from SPI, could someone shed some light on whats actually going on?

5. On the XK-1A schematic, why are two signals multiplexed together? And what is the signal TDOC? I would assume that if the devices were chained together then TDI would go into the device and then TDO from that device would be output to the next so that they could be chained together but TDO is being multiplexed which completely throws me off.

6. In the XS1-L2 example schematic (https://www.xmos.com/published/xs1-l2-1 ... ?support=1) the oscillator that is used is HUGE (ABLS2), is there any reason why this configuration of the oscillator is used as apposed to using something like that used on the XC-1A (Top of Page 2 https://www.xmos.com/published/xs1-l2-1 ... ?support=1)? Are there any constraints on the type of oscillator used or the circuit configuration to make the PLL happy?

7. Ok so this one isn't a question, but I'm pretty sure there is a minor mistake in the datasheet. I noticed that in the XS1-L1 (48pin and 64pin) datasheet, the PLL_AVDD is of type GND and the PLL_AGND is of type PWR which is backward.

If you know an answer could you explain it in as much detail as possible. I've worked with embedded systems but a lot of this is brand new to me, especially interfacing with JTAG. THANK you guys in advance for the help!!


Top
Offline Profile View all posts by this user  
 
PostPosted: Tue Feb 28, 2012 10:44 am 
User avatar
Member
Joined: Thu Jan 26, 2012 1:25 pm
Posts: 15
DrNO - I think I can help some. You ask good questions, I too am curious on some of these details.

1. DNP = Do Not Populate. I haven't studied the design in detail to explain why.

2. Studied this, but unsure.

3. The four signals, I presume, have buffers because the signals are identical on all boards. As the signals passes through the boards from one connector to the next it is "tapped off" to go to the IC. The buffer is used to isolate these four signals from the line shared by all XK-1A that may be connected together.

4. In the processor data sheets I've read the explainations for the JTAG and the four boot pins. Have you seen these sections? I think the boot modes are explained well, and I agree in the combination with MODE(2:3) tied together it must take a board modification to boot via an XLINK.

5. I beleive the multiplex is used because it is NOT true that TDO from one goes to TDI of the next. That is, I was thinking that JTAG2 is only talking to one processor at a time. Anyone with more experience want to chime in?

_________________
Timothy D. Swieter, P.E.
http://www.Brilldea.com
http://www.tdswieter.com


Top
Offline Profile View all posts by this user  
 
PostPosted: Tue Feb 28, 2012 4:13 pm 
User avatar
XCore Expert
Joined: Sun Jul 11, 2010 1:31 am
Posts: 675
DrNO wrote:
1. On PAGE 2 of the L1 USB Audio Schematic (https://www.xmos.com/download/public/USB-Audio-2.0-Ref-Design-XS1-L1-Schematics(1.2).pdf), I noticed that the USB receptacle has 6 pins and I'm confused as to what pins 5 and 6 are. Also the resistor that's connected to both of these pins doesn't have a value and only marked as 'DNP'. Could someone explain this?

That's the shield. The capacitor is there to make hotplug less
sparkly ;-)

Quote:
2. I noticed that on the XK-1A shematic (PAGE 13/15 in https://www.xmos.com/download/public/XK ... Manual(1.0).pdf) there isn't a delay on the RST_N pin like I would expect from the minimum requirements so that VDDIO and VDD could come up before RST_N. How is this taken care of?

Both RST_N and TRST_N have a capacitor to ground and a pull-up
resistor. This is your delay. TRST releases first, as it should.
If you are less lazy than I am you can calculate how long of a
delay this is.

Quote:
3. Also on the same schematic, I have no idea why buffers are used in this way. Could someone explain why they are used and why they are used on on the 'TRST_N', 'TMS', 'TCK', and 'RST_N' pins?

Those are Schmitt triggers actually, not plain buffers. They
condition the signal; you can run the JTAG faster with them
than without. It might also reduce the load on shared signals
like the clock (look in the datasheets to see if this is reallytrue).

Quote:
4. I've noticed in a lot of schematics tie the MODE(2:3) pins together (XK-1A schematic). However, this creates a problem if you wanted the devices to boot via XLink B. Could someone explain the use of TRST_N on these two pins, does it just idle low when plugged into the board? I'm guessing that the pins are pulled up so that when the JTAG isnt' connected then the device boots from SPI, could someone shed some light on whats actually going on?

The MODE pins are sampled at RST_N time only. TRST_N has a
pull-up. If nothing is pulling it low, you get MODE=11, i.e.
SPI boot; if the debug adapter holds TRST_N low while toggling
RST_N, you get MODE=00, "JTAG boot" (really "no boot").

If you want TRST_N to select between boot from link (MODE=10)
and JTAG boot, you would connect MODE3 to TRST_N and MODE2
to ground. But this isn't terribly useful, you can just as
well wire it up to always boot from link (the only effective
difference is that you have some links enabled on the switch,
which is harmless; the reason you do not want to boot from
SPI when loading a program via JTAG is that before you have
the chance to "break in", it will run the program on your SPI,
which can do all kinds of nasty things with I/O etc.)

Quote:
5. On the XK-1A schematic, why are two signals multiplexed together? And what is the signal TDOC? I would assume that if the devices were chained together then TDI would go into the device and then TDO from that device would be output to the next so that they could be chained together but TDO is being multiplexed which completely throws me off.

TDOC comes from the "slave" XSYS controller. The MUX routes
the JTAG chain through the slave XSYS if there is anything
plugged in there, and not if not.


Segher


Top
Offline Profile View all posts by this user  
 
PostPosted: Thu Mar 15, 2012 5:50 am 
Joined: Mon Feb 06, 2012 11:42 pm
Posts: 29
Hey guys.. i forgot to reply with a thank you :oops: . THANK YOU that helped so much!


Top
Offline Profile View all posts by this user  
 
Display posts from previous:  Sort by  
Post new topic Reply to topic   [ 4 posts ] 


Who is online

Users browsing this forum: No registered users and 1 guest



Search for:
Jump to: