1. On PAGE 2 of the L1 USB Audio Schematic (https://www.xmos.com/download/public/USB-Audio-2.0-Ref-Design-XS1-L1-Schematics(1.2).pdf
), I noticed that the USB receptacle has 6 pins and I'm confused as to what pins 5 and 6 are. Also the resistor that's connected to both of these pins doesn't have a value and only marked as 'DNP'. Could someone explain this?
That's the shield. The capacitor is there to make hotplug less
2. I noticed that on the XK-1A shematic (PAGE 13/15 in https://www.xmos.com/download/public/XK ... Manual(1.0
).pdf) there isn't a delay on the RST_N pin like I would expect from the minimum requirements so that VDDIO and VDD could come up before RST_N. How is this taken care of?
Both RST_N and TRST_N have a capacitor to ground and a pull-up
resistor. This is your delay. TRST releases first, as it should.
If you are less lazy than I am you can calculate how long of a
delay this is.
3. Also on the same schematic, I have no idea why buffers are used in this way. Could someone explain why they are used and why they are used on on the 'TRST_N', 'TMS', 'TCK', and 'RST_N' pins?
Those are Schmitt triggers actually, not plain buffers. They
condition the signal; you can run the JTAG faster with them
than without. It might also reduce the load on shared signals
like the clock (look in the datasheets to see if this is reallytrue).
4. I've noticed in a lot of schematics tie the MODE(2:3) pins together (XK-1A schematic). However, this creates a problem if you wanted the devices to boot via XLink B. Could someone explain the use of TRST_N on these two pins, does it just idle low when plugged into the board? I'm guessing that the pins are pulled up so that when the JTAG isnt' connected then the device boots from SPI, could someone shed some light on whats actually going on?
The MODE pins are sampled at RST_N time only. TRST_N has a
pull-up. If nothing is pulling it low, you get MODE=11, i.e.
SPI boot; if the debug adapter holds TRST_N low while toggling
RST_N, you get MODE=00, "JTAG boot" (really "no boot").
If you want TRST_N to select between boot from link (MODE=10)
and JTAG boot, you would connect MODE3 to TRST_N and MODE2
to ground. But this isn't terribly useful, you can just as
well wire it up to always boot from link (the only effective
difference is that you have some links enabled on the switch,
which is harmless; the reason you do not want to boot from
SPI when loading a program via JTAG is that before you have
the chance to "break in", it will run the program on your SPI,
which can do all kinds of nasty things with I/O etc.)
5. On the XK-1A schematic, why are two signals multiplexed together? And what is the signal TDOC? I would assume that if the devices were chained together then TDI would go into the device and then TDO from that device would be output to the next so that they could be chained together but TDO is being multiplexed which completely throws me off.
TDOC comes from the "slave" XSYS controller. The MUX routes
the JTAG chain through the slave XSYS if there is anything
plugged in there, and not if not.