XCore Exchange

Altium Designer library attached.
Use at your own risk! I cannot be held responsible for errors in the library.

Edit: updated files to fix a small mistake.

What TSCM processing node can we expect for the 700 MHz device.
Will the I/O voltage be different and will it use other I/O voltage than 3.3V ?

lilltroll wrote:What TSCM processing node can we expect for the 700 MHz device.
Will the I/O voltage be different and will it use other I/O voltage than 3.3V ?

I'm not authoritative but I think it is still TSMC 65nm.
The 700MHz devices will be the same as the 500MHz, XMOS just guarantees that they can run on 700MHz. Just like the 400 and 500MHz speed bins on the L series.

Thats a very nice chip there, finally some ADCs in it as well as the 700MIPS,damn thats speedy.

One thing i don't like about the package tho is that its BGA, Well it is better than that weird dual row QFN on the L2. But it has under 100 pins, if you put that in tiny pin pitch TQFP it wouldn't really be that big while making the chip much easier to use (Can be made with cheep 2 layer boards, can be soldered without special tools or paying someone to do it)

EDIT: Also why are there so few ports on the pins of it, especially 1bit ones? Most of the IO seams to be that huge 32bit port thats not nearly as useful.

I think it is a 'marketing chip'

Although I don't have any real figures I would imagine that the revenue coming in the door at Xmos is mostly from the digital audio market place, thus any new silicon would likely be targeted at expanding their current success here. Clearly the port structure the new XS1-SU1 offers is ideal for increasing market share within that sector by reducing BOM cost for current and potential Xmos customers while of course leaving out certain other pro features.

I also believe there are some camps inside Xmos that believe (quite rightly IMHO) that they have an opportunity in the high end Micro controller market, unfortunately Xmos have not had a suitable product for this market.

Thus I think what has happened here is some clever person in marketing had a brainwave off putting both of these divergent ideas into a single package. That would explain the addition of the 12 bit ADC (completely useless in the audio market) this is a key micro controller feature. So the result I think is a hybrid or graft depending on your viewpoint, it could be a centaur or hippacrocapig only the market will decide. As for the package, I have never understood why Xmos choose the packages that they do, it baffles me to be quite honest, perhaps someone from Xmos can shine some light on that?

However I really do like some of the features on the new series and I have one project that I am working on which I think it may be near perfect for, although construction around the BGA chips is going to cause me a few nightmares and raise a few eyebrows in the market place that I am building it for.

I am also finding that designing a stamp board for it is rather awkward, so any other suggestions on that front are truly appreciated, this could help others get working with the new chips.

Overall I am pleased with the new direction, hopefully this series will also produce versions with better port choices and packages as time goes by, it would be nice to get some more info on what is possible from the s range or 3rd gen of XS1?

;)

regards
Al

Bianco,

I'm creating an XS1-SU1 Pulsonix part, based on your preview.jpg file, and there seems to be a couple of missing pins - I make it 94 pins in total on those three gates. It should total 96 pins.

Leon you are right that there is something wrong: Wake signal is missing.
I will recheck when i'm back at home (i count 95 pins here on my first attempt)

It might be SW1, VOUT or PGND dupes I think they got me when I did the Eagle parts

regards
Al

I've created a spreadsheet based on the pin configuration diagram, it's attached to this post. It should help avoid mistakes when creating PCB parts, and speed up the process.

I just noticed an error, which I've corrected.

I found the missing pin with the help of my spreadsheet (there was only one). It is WAKE, pin G1, as Bianco thought.

I've also attached my schematic (just the XS1-SU1 symbols).

I have updated my Altium lib: https://www.xcore.com/forum/viewtopic.p ... 442#p11442
I have also checked whether all pins match the right balls, so this time it should really be without errors.
Just need to fix the pin directions some day.