ClassD PWM Questions
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Woody
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What's your reference clock speed? Have you changed it to 400MHz from 100MHz? perhaps you've not changed DEF_REF_FREQ_MHz?
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Andy
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DEF_REF_FREQ_MHz is set to 100. Is this correct?
Would reducing the reference from 400 to 100 mean I'd have to receive samples at 1/4 the rate?
Would reducing the reference from 400 to 100 mean I'd have to receive samples at 1/4 the rate?
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Woody
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Yes, if your reference clock is running at 100MHz (which it will be unless you've changed it).Andy wrote:DEF_REF_FREQ_MHz is set to 100. Is this correct?
No, you just get less granularity on PWM pulse widths.Andy wrote:Would reducing the reference from 400 to 100 mean I'd have to receive samples at 1/4 the rate?
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Andy
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I've been doing some experiments with different delays and DEF_REF_FREQ_MHz but none seem to be getting me the correct results.
When the send delay is PWM_PERIOD_44100 and DEF_REF_FREQ_MHz 100, I get overflow. However, when I change DEF_REF_FREQ_MHz to 200 and the delay to (PWM_PERIOD_44100 * 2) I get normal speed/pitch audio but only the right channel is playing out both speakers.
I've double checked the samples and they're definitely being split off correctly in audioManager()... I'm a bit stuck on this one.
When the send delay is PWM_PERIOD_44100 and DEF_REF_FREQ_MHz 100, I get overflow. However, when I change DEF_REF_FREQ_MHz to 200 and the delay to (PWM_PERIOD_44100 * 2) I get normal speed/pitch audio but only the right channel is playing out both speakers.
I've double checked the samples and they're definitely being split off correctly in audioManager()... I'm a bit stuck on this one.