I know this is an old thread & I hope people don't mind me resurrecting it but I'm currenty trying to get to grips with the bit masking used in this clocking
I think I have a handle on BCLK bit masking - it defines the clock cycle of BCLK in relation to MCLK clock cycle of ?
As the XMOS dcomentation states
The bit clock is generated by performing outputs of a particular pattern to p_bclk to toggle the output at the desired rate. The pattern depends on the divide between MCLK and BCLK. The following table shows the pattern for different values of this divide:
Divide Output pattern Outputs per sample
2 0xAAAAAAAA 2
4 0xCCCCCCCC 4
8 0xF0F0F0F0 8
In other words a divide 8 uses the bit mask 0xF0F0F0F0 or the bit pattern (1111 0000 1111 0000 1111 0000 1111 0000)
If I understand this correctly this BCLK will be high for 4 MCLK clock cycles, then low for 4 MCLK clock cycles, etc.
Divide by 4 gives this bit pattern 1100 1100 1100 1100 1100 1100 1100 1100 or BCLK high for 2 MCLK clock cycles, low for 2 MCLK clock cycles, etc
LRCLK bit masking is just a set bit allocation:
For I2S 0x7fffffff followed by 0x80000000 - both repeated
For RJ 0xffffffff followed by 0x00000000 -repeated
The requirement in this thread was to code for 24 bit RJ sample output - does this not require:
0xFFFFFF & 0x000000 bit patterns for LRCLK
BUT also changing the loops in audio.xc from 32 to 24?
Edit: Is the following code correct (& what's the function of @ tmp)? :
p_lrclk @ tmp <: 0xFFFFFF00; /* 24 bit in 32 bit frame LJ bit-mask ?? */
p_lrclk @ tmp <: 0x00FFFFFF; /* 24 bit in 32 bit frame RJ bit-mask ?? */