audio clocks [SOLVED]

[hafwil]

Hi,I am designing a prototype for an audio board using the xmos startkit.I need one stereo channel output, one mono output and 3 stereo channels input. Sample rate should be fixed, 96kHz or 192kHz. I am using the CS42448 audio codec. I do NOT need any USB audio. Additional there is an external bluetooth chip with SPDIF or I2S output, 48kHz sample rate. The software should then mix all the inputs and the signal from the BT chip in some way and route the audio signal to the outputs. I have finished all the analog parts, the supplies and so on, but now I have troubles to understand requirements for the clocks. I looked at the 8soundusb board, they use a CS2300 PLL, but how do I get the SYNC_OUT, is it enough to simply generate a clock in source code, or is it derived somewhere from the USB audio? I also looked at the USB Audio 2.0 Ref Design XS1-L1 schematics, I think using a single oscillator with appropriate frequency for 96 or 192kHz would be the simplest solution?The bluetooth chip has a SPDIF and an I2S interface, sample rate is fixed at 48kHz. I would like to use the SPDIF output and simply connect it to a port on the XMOS of the startkit and decode it with the SPDIF receiver api available on github. Is it necessary to provide some clock for this to work?Using the I2S interface of the BT chip would require another clock for the 48kHz?Thank you for your help,wilRead

[hafwil]

The Bluetooth Chip is the Wt32i from Bluegiga: http://www.mouser.com/ds/2/52/Bluegigga ... 340990.pdf
The S/PDIF RX component: https://github.com/xcore/sc_spdif
Attached is the schematic for the USB 2.0 Audio Ref Design XS1-L1

More precise questions:

• can I use one clock (24.576MHz) for I2S to drive the audio codec (IN+OUT) at fixed sample rate of 192kHz or 96kHz, like in the attached schematic
• can I simply connect the S/PDIF output signal from the BT chip to a one bit port of the XMOS to let the library decode the 48kHz audio data, or is there some reference clock necessary

An example application can be:
1) decode SPDIF audio stream (48kHz) from BT chip
2) sample stereo audio data (Channel 1 + 2 from codec) with fixed 192kHz
3) upsample BT audio data and mix it with stereo data from codec
4) write mixed signal to codec
or another:
1) sample 3 x stereo audio data (channel 1-6 from codec) with 192kHz
2) mix it
3) create mono signal
4) write mono signal to a single output channel from codec

[infiniteimprobability]

OK - so sounds like you want to listen to the SPDIF input from the module. That's fine. That means the whole system will need to be synchronous to the clock encoded in this stream.

FYI, The existing USB audio ref deisgn supports this (multichannel with SPDIF input) although the updated version is still at beta but being released shortly (so I understand).. However you're not using USB Audio so you can build it up as you choose - I would recommend checking the USB code though as it shows the clock_gen section which gets the sample rate and drives the PLL and provides a small FIFO.

You will need synchronous sample rate conversion (48->96/192) somewhere which could be as simple as sample repetition or more sophisticated using a filter.

More precise questions:
can I use one clock (24.576MHz) for I2S to drive the audio codec (IN+OUT) at fixed sample rate of 192kHz or 96kHz, like in the attached schematic

No - you will need to generate the system MCLK from received SPDIF stream via a PLL, so that everything is in synch, else you need ASRC.

can I simply connect the S/PDIF output signal from the BT chip to a one bit port of the XMOS to let the library decode the 48kHz audio data, or is there some reference clock necessary

Basically, yes. SPDIF Rx is quite clever - it will do all of the work for you and just output L/R samples at the correct rate. You will however need to extract the sample rate and drive the PLL to generate the MCLK. All very doable however and certainly feasible, and within a single tile device.

[hafwil]

Hi! thank you for your help, I understood the problem now and finished the pcb.

I use a PLL now, then I connected both the SPDIF output and the I2S Master interface from the BT chip to the XMOS, so I can evaluate what works best for me.