XCoer 200 Ethernet issue - Lib Ethernet pins configuration

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lokesh327
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Posts: 29
Joined: Wed Feb 06, 2013 2:24 pm

XCoer 200 Ethernet issue - Lib Ethernet pins configuration

Post by lokesh327 »

Hi,

I am working on Xcore 200 board and trying to stream audio using spdif rx pins.

Using the AN00202_gige_avb_i2s_demo sample application, I try to integrate spdif rx module.

I noticed a issue now like hardware manual shows that ibit port XS1_PORT_1O is defined for spdif rx but the same pic was used as clock in lib ethernet module.

portion of code from ethernet.h file

rgmii_ports_t rgmii_ports = on tile[1]: RGMII_PORTS_INITIALIZER;

typedef struct rgmii_ports_t {
in port p_rxclk; /**< RX clock port */
in buffered port:1 p_rxer; /**< RX error port */
in buffered port:32 p_rxd_1000; /**< 1Gb RX data port */
in buffered port:32 p_rxd_10_100; /**< 10/100Mb RX data port */
in buffered port:4 p_rxd_interframe; /**< Interframe RX data port */
in port p_rxdv; /**< RX data valid port */
in port p_rxdv_interframe; /**< Interframe RX data valid port */
in port p_txclk_in; /**< TX clock input port */
out port p_txclk_out; /**< TX clock output port */
out port p_txer; /**< TX error port */
out port p_txen; /**< TX enable port */
out buffered port:32 p_txd; /**< TX data port */
clock rxclk; /**< Clock used for receive timing */
clock rxclk_interframe; /**< Clock used for interframe receive timing */
clock txclk; /**< Clock used for transmit timing */
clock txclk_out; /**< Second clock used for transmit timing */
} rgmii_ports_t;

#define RGMII_PORTS_INITIALIZER { \
XS1_PORT_1O, \
XS1_PORT_1A, \
XS1_PORT_8A, \
XS1_PORT_4E, \
XS1_PORT_4F, \
XS1_PORT_1B, \
XS1_PORT_1K, \
XS1_PORT_1P, \
XS1_PORT_1G, \
XS1_PORT_1E, \
XS1_PORT_1F, \
XS1_PORT_8B, \
XS1_CLKBLK_1, \
XS1_CLKBLK_2, \
XS1_CLKBLK_3, \
XS1_CLKBLK_4 \
}

can someone suggest me why was this port used for ethernet and is there any alternative to using this spdif rx port to read spdif data.

Thanks
Lokesh


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larry
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Joined: Fri Mar 12, 2010 6:03 pm

Post by larry »

In addition to the external clock, data, SMI and CTL ports, some ports are used internally when RGMII is enabled (see datasheet section "RGMII"). This includes ports 1O and 1P that are wired to optical and coaxial S/PDIF on the MC AUDIO board. This means that you can't use S/PDIF and Ethernet together on that board.

You could use pin headers to connect an external S/PDIF receiver. For example xDAC_SD and xSDIO on tile 0.
lokesh327
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Posts: 29
Joined: Wed Feb 06, 2013 2:24 pm

Post by lokesh327 »

Hi,

this means if I configure the pins on tile 0, then can i use the builtin SPDIF RX port on xcore 200 to get data or you mean to connect externally and transfer data on xcore 200 using these pins.

Thanks
lokesh
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