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/* Master clock defines (in Hz) */
#define MCLK_441 (512*44100) /* 44.1, 88.2 etc */
#define MCLK_48 (512*48000) /* 48, 96 etc */
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#define MCLK_441 (512*44100) /* 44.1, 88.2 etc */
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#define MCLK_441 (1024*44100) /* 44.1, 88.2 etc */
so whether my changes is not enogh for a higher mclk?
my firmware: 6.15.2
my board: xCORE-200 eXplorer
my app: app_usb_aud_xk_216_mc
my configure: 2xoxx