Porting ASRC to XS1 processor
Posted: Thu Feb 07, 2019 11:43 pm
Whoever is anyone is familiar with AN00231 SPDIF-Receive-to-I2S-output-using-ASRC x->192kHz:
Can you give any guidance on the possibility of porting the ASRC to XS1? I see that dual issue instructions are used in critical loops. Looking at the benchmark data and reading some of the other discussions of the ASRC, I assume it would take some work to separate some pieces of the operation into more threads/cores.
I wonder if there was an initial coding of the project that wasn't optimized with dual-issue instructions or if it was dual-issue critical loops from the beginning.
thanks
Can you give any guidance on the possibility of porting the ASRC to XS1? I see that dual issue instructions are used in critical loops. Looking at the benchmark data and reading some of the other discussions of the ASRC, I assume it would take some work to separate some pieces of the operation into more threads/cores.
I wonder if there was an initial coding of the project that wasn't optimized with dual-issue instructions or if it was dual-issue critical loops from the beginning.
thanks