I am going to use XL216 series chip to do the work of AD acquisition, AD model is AD7768, the AD data clock frequency is 8M, (125ns); 32 data patterns, I sample while DRDY signal is high, adopt 1 port 32 bit to buffer AD data. Taken every 32 clocks.
Since the DRDY signal time is only about 40 ns, and the sampling statement executes about 10 ns per step, the data in the following several channels is misaligned. I would like to know if eight channels can be sampled at the same time.
Code: Select all
on tile : clock clk = XS1_CLKBLK_1;
on tile : in port p_clk_in = XS1_PORT_1I;//using external AD CLK
on tile : in port p_rd = XS1_PORT_1J;// DATA READY SIGNAL
on tile : in buffered port:32 chan_1 = XS1_PORT_1L;//DATA CHANNEL
on tile : in buffered port:32 chan_2 = XS1_PORT_1K;
on tile : in buffered port:32 chan_3 = XS1_PORT_1M;
on tile : in buffered port:32 chan_4 = XS1_PORT_1N;
on tile : in buffered port:32 chan_5 = XS1_PORT_1O;
//wait for data ready signal which last about 40ns. it's not enough.
case p_rd when pinsneq(0):> cmd:
//here time is not enough for me to capture all data ,so the next channel is wrong.
Here is some result : Channel 3 is right ,and the chan-4 is wrong .because I clearbuf one bit after sampling.
the channel : 3 , the volt is 2.166507
the channel : 4 , the volt is 2.166013
the channel : 4 , the volt is 4.213932