XCore Exchange

Hello.
I am beginner.
I have a question.

I want to change to xe216 from xs1_l2.
I am modifying the base of XR-AVB-LC-BRD.xn.
How to change Port Location ?
ex) what is Port number for PORT_ETH_RXCLK?

YEAH - the forum is operational again :)

Hi. A few quick pointers:

1) The XS1 based design does not contain an internal Ethernet PHY. Respectively, the PHY is external and is mapped to the XMOS CPU using the referenced GPIO pins which bit-bang like mad to chat with the external hardware. You will have to make a decision if you wish to use the same IP with an external (same) PHY to keep it simple for your design. While it is not often super critical to use the same port pins as the XS1 on your new CPU, it will make start up of the new design less of a pain. Do however, maintain the same bit width as the original if taking this approach.

This means that if you see say P1A in the original design, the "1" is a SINGLE BIT port so you must locate a similar "1" bit port on the XS2 = aka XCORE-200 CPU you are about to target.

Also, you are using a DUAL tile CPU for the new target. This means that X0 prefix = Tile #0 where X1 = Tile # 1 and so on if you had applied a 4 TILE CPU. Again for sanity, keep the ports on the SAME tile to keep this migration simple.

2) Plan B is to forget about the XS1 Ethernet PHY and applied the PHY are your already paying for inside the XE series of the XCORE-200 CPU. However, for this solution, you will have to review and apply the Ethernet coding intended for the new target. Pretty sure the XCORE-200 is well maintained by XMOS as that is the current baby of their silicon.

In summary, the XMOS CPU is a bunch of hyper speed GPIO pins. There are some pros/cons to using the different port widths (ie. 1, 4, 8, 16, 32 wide ports). For clock ports, you MUST use single bit ports only. That is a restriction.

If possible, post your mappings for a review by others who have worked with the Ethernet functions before designing a custom PCB. Often small but life sucking errors can be caught early in the design cycle.

Hop this gibberish helps a bit.