Plausibility estimation required

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ataradov
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Plausibility estimation required

Postby ataradov » Fri Jun 11, 2010 7:01 pm

I have one project in mind that I know how to approach with FPGA, but I'd like to try something new. I'll do my best reading documentation on weekend, but just in case I'll miss something can someone estimate if my project will fit any Xmos device and which one if it will.

Here it goes: project is something like DSO - 8 bit ADC (10 - 60 MHz clock rate), around 512k of SRAM (or more of SDRAM, if possible), USB connectivity to transfer data to the PC (low speed is enough really).

Xmos device is supposed to do the following: provide clock signal to the ADC, read data from the ADC, store it to the SRAM, compare received data to some trigger value in (real time), stop acquisition as trigger condition is met.

So is there any Xmos device that are capable of performing such tasks and if not which parameters are hard to achieve so I could correct them, if possible?
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monk_is_batman
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Postby monk_is_batman » Fri Jun 11, 2010 10:22 pm

I can't address your entire project but I can definitely touch on some of the pieces to give you an idea of where it stands.

ADC - I think reading from the ADC is definitely doable, I've read from lines at 12 MHz before, and I've seen SPI code run at 25 MHz, I'm not sure you can get the full 60 MHz out of it, but you can definitely fall within the range.

512k of SRAM - Not really sure on this I've seen a couple threads about this here, the problem I think is the number of Pins involved, the XMOS is capable of talking to it, I just question whether you will have the i/o pins on a single core broken out on a dev board. - The XC-1A has 4 Mbits of onboard flash (not sram) that could be used hypothetically, but I haven't measured the speed on that.

I have a XC-1A, which is a great little dev board that may be a little overpowered for this task but would do the job. It has a ftdi chip on it that converts USB data to UART, which makes communicating with the computer really easy. I'm told it can transfer at up to 3Mbps, but I've personally only bothered driving my up to about 1 Mbps, XMOS provides code that will do 1 Mb for you.

If the XMOS looks like it will work out for you (which I think it will) then I highly recommend that you use it. The programming for it is alot of fun and the architecture never ceases to amaze me.
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lilltroll
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Postby lilltroll » Fri Jun 11, 2010 10:37 pm

Hmm, since I was playing with SRAM yesterday, here comes some thoughts.

If you use a Async 10 ns 256k x 16 -> 1M X 16 SRAM for an example, you can write 2 samples on the same time, using the 32-bit port for adress control and a 16-bit port for data. If you need to change the R/W pin all the time you would maybe drive it from the same 32-bit port to be able to save an instruction, but otherwise use a 1 bit port.

USB/Ethernet - there is 2 chips that is used very often for this. For low speed, UART over USB with an FTDI chip is also possible.

ADC clock. I would consider a clock synthesizer. For an example the one that is used on the XAI bord, that can provides any low-jitter clock from 6-75 MHz.

Ckeck out this master thesis
6_rxEcsORyU

http://archive.xmoslinkers.org/node/284
Probably not the most confused programmer anymore on the XCORE forum.
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lilltroll
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Postby lilltroll » Fri Jun 11, 2010 11:30 pm

Ohhh, I missed that all port types can be FIFO buffered. But you cannot change data direction on the fly. But you do not need that.
Everything is re-sampled internally "Note that any external clock is itself clocked-in using the 400 MHz core clock."
If you let the XMOS create the clock signal (master), it can only produce a new flank every 10 ns => 50 MHz square wave. But using an external clock changes things (XMOS becomes the slave to data).

With an external clock source I guess that you can receive any speeds up to 100M flanks per second? (I'm not sure or is it 400Mflanks or is it 50M flanks ?)
With the double-buffering FIFO enabled you are also able to process the data.


3.1.1 FIFO
A double-buffering FIFO can be enabled on for 1, 4, 8, 16, and 32-bit ports.
The FIFO serialises (output) or deserialises (input) data. The double buffering
allows the entire contents of the FIFO to be copied for transfer to (input) or from
(output) the program. This enables data to be serialised using a high-frequency
clock decoupled from the program.
The FIFO holds at most bpw bits; this enables a single word-wide operation to
transfer the entire contents of the FIFO to or from a register. Hence, for a w-bit
wide port, the size of the FIFO is limited to bpw
w elements. The topmost w bits of
the FIFO are the value that is most recently clocked in. The lengths of the FIFO
that are supported are:
• 1-bit ports: 4, 8, 32.
• 4-bit ports: 8 (2 elements), 32 (8 elements).
• 8-bit ports: 32 (4 elements).
• 16-bit ports: 32 (2 elements).
• 32-bit port: double buffering only.
Probably not the most confused programmer anymore on the XCORE forum.

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