XCore Exchange

Lib_usb-[sw]_3.1.2rc2 is the USB library. Looked at the PDF document, it seems that there is no explanation, or that there is no limit to the number?
Thank you!

for the Bulk endpoint type

Hi. Believe the limit is max value of 6 endpoints.

See section 1.4 of this document:

https://www.xmos.com/developer/download ... rc4.a).pdf

It's a little unclear for sure but the way I read it, it needs 1 core for XUD, 1 core for EP0 (which can't be bulk), and 1 additional core per EP. With the limit that no more than six cores may be used on the USB tile, and all EP cores must be on the same tile as XUD, that leaves 4 free cores. So that would imply up to 4 bulk endpoints could be possible... but I might be wrong.

We have multiple products that use all 8 "cores" on the XUD "tile". It seems to me that the published limitation of 6 cores used on an XUD tile is a very rough guideline. Clearly there is a big difference in processing load between running a single UAC endpoint with 2 channels of max 192kHz FS vs 2 UAC endpoints running 8 channels each at 192kHz (up and down). I think you just have to test your design thoroughly and be sure you're not saturating the tiles execution cycles.

And, I don't see why all EP cores must be on the same tile. I know that the UAC reference software project relies on "global variables" - a lot of transfer of data and flags are transferred between "cores". You'd have to clean-up the way data is transferred between threads (um "cores") - move all data transfers to channels and channels move data to other tiles.

Maybe not relevant to you unless you're running UAC - but the decouple() thread can be significantly optimized to reduce execution cycles. It has a continuously spinning loop that could be blocked with a hand-tuned timerafer - or maybe a more clever method. But that would free-up a lot of execution cycles on the XUD tile for another endpoint.

akp wrote:It's a little unclear for sure but the way I read it, it needs 1 core for XUD, 1 core for EP0 (which can't be bulk), and 1 additional core per EP. With the limit that no more than six cores may be used on the USB tile, and all EP cores must be on the same tile as XUD, that leaves 4 free cores. So that would imply up to 4 bulk endpoints could be possible... but I might be wrong.

Um, yeah. But the OP was referring to bulk endpoints, not UAC (UAC endpoints should be isochronous, right? perhaps that fact can be leveraged to improve efficiency, who knows? I don't.) Furthermore, the OP didn't mention modifying the underlying XMOS code to improve efficiency. So I just interpreted the admittedly conservative recommendations from XMOS; I haven't tested it. If that's not enough then I am sure the OP will appreciate your excellent suggestions to improve efficiency or move on to another vendor.

It is really a nice post.