Interfacing Quad SPI flash to an XMOS device

[Folknology]

Heater

I'm not sure about XIP on ARM can't find references, but as you say for virtual machines or interpreters etc.. Quad SPI flash is handy. However you still have to deal with branching issues/caching/look-ahead how are you dealing with that for ZPU?

regards
Al

[leon_heller]

Schematic looks good to me Leon

There are 2 spare 1 bit pins, any ideas for using them?

Put them on a jumper maybe with 3.3v & Gnd

regards
Al

What would that give us? I did think of an LED.

I've added the second ground connection, and labeled the spare pins.

[Heater]

Folknology,

Basically the ZPU on the Prop ignores all issues of memory access. That has be delegated to external memory interface drivers. Those drivers run on a different core to the ZPU virtual machine itself and communicate memory read/write commands through a "mailbox" in on chip RAM. I have left development of those drivers up to others.

So far there are two different external memory drivers. Both of them implement some form of caching via different algorithms and both of them support a variety of different memory types, SRAM, SDRAM, SPI etc. To be honest I have not looked very deeply into how those drivers handle caching.

[leon_heller]

My PCBs have been made and are on their way to me. I should get them in a day or two. Those are the original single-chip breakout board ones.

[mikronauts]

Hi Leon,

Did you get the QSPI chips working?

I am sitting next to some Xmos dev boards, and I have QSPI Winbond chips in my parts cabinet...

Regards,

Bill

[jmg]

?? It is not clear if this ever got finished ?
I'd be interested in the MHz achieved, and the code, if it ever was able to work ?

[leon_heller]

I forgot about it. I came across one of the little PCBs I designed the other day with one of the chips mounted on it, I ought to resurrect the project. I've got several of the PCBs, if anyone wants one.

[jmg]

I forgot about it. I came across one of the little PCBs I designed the other day with one of the chips mounted on it, I ought to resurrect the project. I've got several of the PCBs, if anyone wants one.

So did you get any MHz numbers on this ?

From my other thread, it seems you cannot easily gate clocks (ie so clk edges match data bits), but I see these data sheet specs on QuadSPI parts Tsu/Th on the CSn and Data lines.

Winbond (104MHz) Tsu CS =5ns Th CS = 5ns Tsu D= 1.5ns Th D = 4ns Tdo = 5ns
Atmel (100MHz) Tsu CS =5ns Th CS = 5ns Tsu D= 2ns Th D = 1ns Tdo = 5ns

These are all relative to the same clock edge, and active read edge is always _/=

The CS is not quite as fast as Di, but it is fast enough to choose the 'right' clock edge at 100MHz
(assumes no skew on outputs of CLK and DATA pins - if both are 400MHz derived, this could be reasonably valid ? )

So it may be possible to use either a data stream, or a timed-widh, to control CSn, and have it
keep predictable timing relative to streaming data edges ?

100MHz may be possible ?

Given the lack of FLASH on XMOS, and the huge and growing presence of Quad SPI memory, it is surprising that XMOS have still not provided a proven/optimised Quad SPI library ?

More and more Microcontroller vendors are delivering QuadSPI support in hardware.

[leon_heller]

I never even interfaced it to anything, and the board still needs a decoupling capacitor and connector adding. I'm just about to do that.

I'll interface it to a Sparkfun XS1-L1-64 board, and see if I can get it doing something.

I only had the one board made, in fact. I can get some more made very cheaply (10 off for $1 each) by ITead Studio in China, if anyone wants one.

[Folknology]

My original idea was to have 2 x quad spi flash chips (running in parallel) on say 2x4bit or 1x8b bit port + 1 bit ports for clk,cs etc.. that way a board could be made to fit the standard 16 pin xmos headers found on XK1,XC1 etc.. I don't have a sparkfun board.

regards
Al