Re: What's all this RISC-V stuff, anyhow?
Posted: Wed Jan 18, 2023 9:28 am
Hi, Thank you for the links. Very instructive. Seems each tile will embody an ALU with FP and Vector unit as in the XS3A, let see if they also introduce additional instruction in RV32IM like the 32x32=64 MACC or LSAT or Lextract on 64 bits dual registers.
Also they have hacked the 32bit encoding instruction so that 2x16 bits instructions can be encoded and executed in parallel. let see in practice how the M/R/M+R/M&R actual constrains are handled in the risc-v world.
What is still not clear to me is how the xcore specificities related to hardware threads (aka HARTS now) and the event based model (instead of usual interrupt) will be formalized in the risc toolsets, as the XC compiler and language would be discontinued. Also the concept of "interface" which simplifies inter-tile communication is "lost in translation". No words on the target software framework during the presentation.
Also they have hacked the 32bit encoding instruction so that 2x16 bits instructions can be encoded and executed in parallel. let see in practice how the M/R/M+R/M&R actual constrains are handled in the risc-v world.
What is still not clear to me is how the xcore specificities related to hardware threads (aka HARTS now) and the event based model (instead of usual interrupt) will be formalized in the risc toolsets, as the XC compiler and language would be discontinued. Also the concept of "interface" which simplifies inter-tile communication is "lost in translation". No words on the target software framework during the presentation.