update of the file in version 14 15 in first post of this topic, now including XU316 in TQ128 package.
interesting to note that the pinout of the XU316 is not identical to XU216, also due to about 10 pins taken for MIPI or voltage selection.
a column is ready on the right end side for describing the AUDIO-MC board pin allocation but couldn't find the all data yet
Q&A Explorer XK-EVK-XU316 and XK-AUDIO-316-MC
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- XCore Addict
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Hi
as un update,
a new web page on xmos.ai is now dedicated to the XK-AUDIO-316-MC, pointing on a new V1.1 for the Hardware Manual with schematics, and a link to download USB audio V7.2.
https://www.xmos.ai/develop/usb-multichannel-audio/
remark regarding AppPLL, the HW manual summarizes the jitter figures in the audio band (page 14)
I have update the port mapping file in the first post of this topic, version 16, with the mapping for the XK-AUDIO-316-MC signals in the last column.
Thanks to the xmos team for achieving the release of the new usb_audio_sw and its port to the XU316
as un update,
a new web page on xmos.ai is now dedicated to the XK-AUDIO-316-MC, pointing on a new V1.1 for the Hardware Manual with schematics, and a link to download USB audio V7.2.
https://www.xmos.ai/develop/usb-multichannel-audio/
remark regarding AppPLL, the HW manual summarizes the jitter figures in the audio band (page 14)
I have update the port mapping file in the first post of this topic, version 16, with the mapping for the XK-AUDIO-316-MC signals in the last column.
Thanks to the xmos team for achieving the release of the new usb_audio_sw and its port to the XU316
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Hi
first post is update with xls file v17
better accuracy of information for the xu316 tq128 columnn and last column presenting the ports and naming used on the XK-AUDIO-316-MC.
in fact when used with USB phy on tile 0, we have 8 usable 1 bits port on tile0 and 16 on tile 1 with some constrains:
Tile 0, 1 bit port available:
first post is update with xls file v17
better accuracy of information for the xu316 tq128 columnn and last column presenting the ports and naming used on the XK-AUDIO-316-MC.
in fact when used with USB phy on tile 0, we have 8 usable 1 bits port on tile0 and 16 on tile 1 with some constrains:
Tile 0, 1 bit port available:
- P1A0, P1M0, P1N0, P1P0 no constrains
P1D0 but ideally reserved for AppPLL or MCLK input
P1G0 but using VDD_IOB_1V8
P1L0 but also used as the unique free xConnect xlink3 (tx1)
P1O0 but also used as MIPI_CLK in case a camera is used on MIPI bus
- P1A0, P1B0, P1C0, P1F0, P1G0, P1I0, P1J0, P1K0, P1L0, P1M0, P1N0, P1O0, P1P0
P1D0 but ideally used for PLL output (or MCLK)
P1E0, P1H0 but using VDD_IOB_1V8
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Hello,
first post updated with version 18 including a column on right side describing pins used on PawPaw board (PXUA-XU316) version 3 according to this schematic:
first post updated with version 18 including a column on right side describing pins used on PawPaw board (PXUA-XU316) version 3 according to this schematic:
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Hi,
In the specs for XK-EVK-XU316 I see 128MB of LPDDR memory. If I flash that board with the sw_usb_audio firmware — will this memory be accessible (for example, for storing audio samples and long impulse responses)?
Thanks.
In the specs for XK-EVK-XU316 I see 128MB of LPDDR memory. If I flash that board with the sw_usb_audio firmware — will this memory be accessible (for example, for storing audio samples and long impulse responses)?
Thanks.
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Hello,
for the time being I couldn't find any open source code for accessing LPDDR.
the ISA architecture document is quite obscur on how the prefetch and flush work, and the data sheets explaining the LPDDR register doesn't help ...
this is possible of course and it seems it is used in the plate-recognition application with tensor flow, but no visibility on this.
you could try raising a support ticket to xmos to get more information under nda
if you build your own board, a QSPI PSRAM device could be an alternative, saving some space and compatible with smaller XU316 device package.
for the time being I couldn't find any open source code for accessing LPDDR.
the ISA architecture document is quite obscur on how the prefetch and flush work, and the data sheets explaining the LPDDR register doesn't help ...
this is possible of course and it seems it is used in the plate-recognition application with tensor flow, but no visibility on this.
you could try raising a support ticket to xmos to get more information under nda
if you build your own board, a QSPI PSRAM device could be an alternative, saving some space and compatible with smaller XU316 device package.
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- XCore Addict
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Hello, regarding LPDDR, there is a recent pdf document here:
https://www.xmos.com/documentation/XM-0 ... -tile.html
where you can download 2 pdf files for tools or programing guide.
see in tools guide chapter 4.6 page 71
here is the pdf for convenience
https://www.xmos.com/documentation/XM-0 ... -tile.html
where you can download 2 pdf files for tools or programing guide.
see in tools guide chapter 4.6 page 71
here is the pdf for convenience
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