Off the top of my head I don't have a good example. I don't want to dwell on emulations much although it does bug me a little that one cannot fit a Z80 emu and 64k CP/M system or a 6809 + FLEX in a single core device:)
But it seems to me that it must be very easy to fill up the available RAM. Over the years I've been involved in many embedded micro projects that ended up scraping around try to find a few more bytes. Whether they started with 4K, or 64K.
NetStamp project
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Heater
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shawn
- XCore Addict
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Perhaps one of the key catalyst for the PC circa. 70-80's era, would be the exploitation of DRAM.
I think the trick to address our address limits is to build said custom smart memory services via.
small super clusters of XMOS cores with like a VLIW memory scheme with a socket full of FastXlinks.
I would like to design custom IP to tag into the Xmos. The main advantage to developing a pure OS
for the Xmos is business. There is a lot of IP and perpetually more via IP2 business.
The art of the Monitor [OS] business would exploit fallout from developers where the developers could exploit there talent even more. Money as a channel for developers would be a cool payoff.Think stock options for example and our software can be hardware. The question I ask is how do you exploit the CSP type of monitor so as to count and conquer IP2. I have a few ideas of my own, mostly black box type of ideas. My most difficult problem as I see it is the power window of choice and then dealing with that limit to develop a holistic Xmos platform for said exploits. Limits as a given rule forces us to think. Oh! and I think I understand why Tony Hoare went to work at MS. To me Tony seams like the ultimate mentor, I couldn't understand his MS decision. After listening to several of his lectures I am starting to understand it as his own personal research into the darkside. MS knows all about CSP and there not about to put said tech in there technology. instead they use it for inside development and characterization. Money moves at the speed of light, CSP would upset, and perhaps even displace there own locked in market. If money not MS or others like her, ever gets CSP they will run fast with it, win win win. Get it! MS fears CSP, I'm not kidding around ...CSP for IP2 exploitation empowers and enables developers and there customers to access the mass of silicon that is out there for healthy consumption. IP2 is amenable to CSP like our favorite chip...
Shawn
PS Netstamp is win win win
I think the trick to address our address limits is to build said custom smart memory services via.
small super clusters of XMOS cores with like a VLIW memory scheme with a socket full of FastXlinks.
I would like to design custom IP to tag into the Xmos. The main advantage to developing a pure OS
for the Xmos is business. There is a lot of IP and perpetually more via IP2 business.
The art of the Monitor [OS] business would exploit fallout from developers where the developers could exploit there talent even more. Money as a channel for developers would be a cool payoff.Think stock options for example and our software can be hardware. The question I ask is how do you exploit the CSP type of monitor so as to count and conquer IP2. I have a few ideas of my own, mostly black box type of ideas. My most difficult problem as I see it is the power window of choice and then dealing with that limit to develop a holistic Xmos platform for said exploits. Limits as a given rule forces us to think. Oh! and I think I understand why Tony Hoare went to work at MS. To me Tony seams like the ultimate mentor, I couldn't understand his MS decision. After listening to several of his lectures I am starting to understand it as his own personal research into the darkside. MS knows all about CSP and there not about to put said tech in there technology. instead they use it for inside development and characterization. Money moves at the speed of light, CSP would upset, and perhaps even displace there own locked in market. If money not MS or others like her, ever gets CSP they will run fast with it, win win win. Get it! MS fears CSP, I'm not kidding around ...CSP for IP2 exploitation empowers and enables developers and there customers to access the mass of silicon that is out there for healthy consumption. IP2 is amenable to CSP like our favorite chip...
Shawn
PS Netstamp is win win win
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Folknology
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Shawn Are you aware that Microsoft's nemesis Google get CSP - Go?
Also the real anchor dragging on the sea floor isn't Microsoft it's Intel, Goog is fixing the M$ issue.
IP2 = distributed IP of the commons, abundance rather than scarcity, the genie is out of the box..
Oh and XSx doesn't need an anchor it can utilise the Force..
So use the Force...
Also the real anchor dragging on the sea floor isn't Microsoft it's Intel, Goog is fixing the M$ issue.
IP2 = distributed IP of the commons, abundance rather than scarcity, the genie is out of the box..
Oh and XSx doesn't need an anchor it can utilise the Force..
So use the Force...
Last edited by Folknology on Sat May 15, 2010 12:32 am, edited 1 time in total.
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shawn
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Now I am, Thanks you for the tip.
Way to be! Google. They have the clout, I'm long on Google.
Developers get Google or should I say Google gets Developers.
I'll check out this GO! GO and XMOS may be a symbiosis.
Shawn
PS Intel can be gone tomorrow, Ill stick the knife in its back
and let you twist it. Or if that's to violent then just hold INTL
down while I step on its throat. Excuse me,, I just came from
the sex and violence posts.
Way to be! Google. They have the clout, I'm long on Google.
Developers get Google or should I say Google gets Developers.
I'll check out this GO! GO and XMOS may be a symbiosis.
Shawn
PS Intel can be gone tomorrow, Ill stick the knife in its back
and let you twist it. Or if that's to violent then just hold INTL
down while I step on its throat. Excuse me,, I just came from
the sex and violence posts.
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lilltroll
- XCore Expert
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- Location: Sweden, Eskilstuna
Added some more components.
You do not have the required permissions to view the files attached to this post.
Probably not the most confused programmer anymore on the XCORE forum.
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shawn
- XCore Addict
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Is it logical to think about using mini Ethernet socket or between cost and or would it be a pointless
in that having to have an adapter might get in the way of just plug and function.
Nice image of the NetStamp, "its a killer!".
shawnster
in that having to have an adapter might get in the way of just plug and function.
Nice image of the NetStamp, "its a killer!".
shawnster
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Heater
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That board does look great. Can't wait to get my hands on one.
That's an interesting observation that "Google gets CSP".
Sure looks like they do. By all accounts they have thousands or hundreds of thousands of processors running even more processes and those processes can communicate. Google's Protocol Buffers are sweet.
BUT don't forget, each one of those processing nodes is a full up Linux running computer with a huge pile of RAM and probably hard drive space. No matter how many XMOS chips you put together in a team it looks like a long way away from being able to do what Google does or anything approaching it.
I think there is some kind of "impedance matching" that goes on between processors and their RAM.
Consider: For any given processor speed and size (8,16,32,64bit) having zero RAM is like a battery with no load, it can't deliver any power (processing rather than watts). Conversely that same processor with an infinite amount of RAM is like a battery driving a short circuit. Especially if the problem it is working on fills that RAM. It can't deliver any power, even though it is working full speed on the problem.
We can see this in the real world. It's kind of pointless adding gigabytes of RAM to a 4Mhz 8bit CPU like a Z80. Any kind of problem that would need gigabytes of RAM, video processing or data base search say, would take forever to run. Conversely shipping the latest Intel 64bit multi-Ghz PC with only 64K of RAM would be all but useless.
Now at some point having "impedance matched" your processor speed and RAM size you might come to the conclusion that increasing performance or tackling bigger problems is best done by having multiple sets of processor and RAM and spilit the problem across the sets. Enter CSP.
It's this impedance matching phenomena that make me feel that having these speedy 32 bit XMOS processors with such limited RAM is a shame.
Shawn, yes indeed, limits make you think. A lot of wonderful things have come about due to people wanting to stuff a quart into a pint pot.
Is that possibly enough "philosophy" for this thread:)
That's an interesting observation that "Google gets CSP".
Sure looks like they do. By all accounts they have thousands or hundreds of thousands of processors running even more processes and those processes can communicate. Google's Protocol Buffers are sweet.
BUT don't forget, each one of those processing nodes is a full up Linux running computer with a huge pile of RAM and probably hard drive space. No matter how many XMOS chips you put together in a team it looks like a long way away from being able to do what Google does or anything approaching it.
I think there is some kind of "impedance matching" that goes on between processors and their RAM.
Consider: For any given processor speed and size (8,16,32,64bit) having zero RAM is like a battery with no load, it can't deliver any power (processing rather than watts). Conversely that same processor with an infinite amount of RAM is like a battery driving a short circuit. Especially if the problem it is working on fills that RAM. It can't deliver any power, even though it is working full speed on the problem.
We can see this in the real world. It's kind of pointless adding gigabytes of RAM to a 4Mhz 8bit CPU like a Z80. Any kind of problem that would need gigabytes of RAM, video processing or data base search say, would take forever to run. Conversely shipping the latest Intel 64bit multi-Ghz PC with only 64K of RAM would be all but useless.
Now at some point having "impedance matched" your processor speed and RAM size you might come to the conclusion that increasing performance or tackling bigger problems is best done by having multiple sets of processor and RAM and spilit the problem across the sets. Enter CSP.
It's this impedance matching phenomena that make me feel that having these speedy 32 bit XMOS processors with such limited RAM is a shame.
Shawn, yes indeed, limits make you think. A lot of wonderful things have come about due to people wanting to stuff a quart into a pint pot.
Is that possibly enough "philosophy" for this thread:)
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shawn
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I just got done watching the GO! video. What a gestalt.
I got a lot rite away ~ Interfaces for Generality, frob itoff a channel, quit from noise, channel on channel, channeling 100,000 controlled possesses in a heart beat. I'm all in. 8-)
Sequential or multiplexed moving the process to the memory in this case the process is a virtual machine, not an emulation jit for compile and debug but a simulation and hopefully self timed to theoretically port across a wide variety of programmable mediums to cmos, instead of memory to the process. There's a heat penalty for virtual memory, infinity divided by nbits is inversely proportional to the static power of that memory or heat to manage dram 2^nth times nbits over nbit all for nbits per cycle. So I guess the question would be what is the optimal impedance of Ram in relation to its instruction set and what scales best before SPI to Sans or off chip via fastlinks via g4 or more and the ram and its physical logic controller that is warranted in relation to power to throughput.
me again
I got a lot rite away ~ Interfaces for Generality, frob itoff a channel, quit from noise, channel on channel, channeling 100,000 controlled possesses in a heart beat. I'm all in. 8-)
Sequential or multiplexed moving the process to the memory in this case the process is a virtual machine, not an emulation jit for compile and debug but a simulation and hopefully self timed to theoretically port across a wide variety of programmable mediums to cmos, instead of memory to the process. There's a heat penalty for virtual memory, infinity divided by nbits is inversely proportional to the static power of that memory or heat to manage dram 2^nth times nbits over nbit all for nbits per cycle. So I guess the question would be what is the optimal impedance of Ram in relation to its instruction set and what scales best before SPI to Sans or off chip via fastlinks via g4 or more and the ram and its physical logic controller that is warranted in relation to power to throughput.
me again
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Heater
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Shawn, after the first paragraph there I absolutely cannot understand any of the rest of that post.
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Folknology
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Shawn/Rowan/Thomas I think the only way we are going to answer that question is to actually "do stuff". That is what we intend doing with NetStamp, by building the Amino stack we have enough depth and width to work out the parasitics of that impedance match.
When we are closer to those results we can appeal to Xmos with our qualified recommendations.
In the meantime we have just knuckle down and do it, find out where those edges are..
When we are closer to those results we can appeal to Xmos with our qualified recommendations.
In the meantime we have just knuckle down and do it, find out where those edges are..