hello dear forum,
i just want to quickly confirm what i read in the documentation, can't be too cautious.
i am using a chip (wm8741 DAC) that uses tri-state logic on input pins for configuration. For example:
MODE/LRSEL pin:
0 = hardware control mode
1 = 3-wire serial control mode
Z = 2-wire serial control mode
The datasheet of xCORE-200 chips mentions open collector outputs where 'L' if '0' and 'Z' if '1'. The xs2 architecture isa document mentions both cases, e.g. this along with 'Z' if '0' and 'H' if '1'. Of course i just need one of those modes to get 'Z'.
And also the pins have weak PD that can be disabled, and should be if i need floating or regular output. this has nothing to do with the pull-up/down drive mode of the port configuration.
So therefore, the required configurations would be like:
0: setc port, CTRL_DRIVE_DRIVE
out port, 0x0000
1: setc port, CTRL_DRIVE_DRIVE
out port, 0xffff
Z: setc port CTRL_DRIVE_PULL_DOWN
out port, 0xffff
or
setc port CTRL_DRIVE_PULL_UP
out port, 0x0000
I want to confirm that i can do this directly with the xmos pins for my case, without the need of an additional tri-state buffer, and that my summary of relevant info is accurate.
xCORE-200 io pins tri-state
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- Experienced Member
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- XCore Legend
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Hi. Please review the comments from Dave Lacey (XMOS) here:
https://www.xcore.com/viewtopic.php?f=3&t=2033
Appears you can configure the GPIO as open drain as you have stated and Dave is showing XC examples of this implementation.
However, best to at least test or leave room for a single gate open-drain buffer in series so that the PCB layout is not wasted if the direct XMOS pin to DAC does not function correctly.
That is, allow for a 0402 or similar 0 ohm to bypass the open drain buffer so that you can stuff either / or to 100% guarantee the design will work. You could even leave room for a 0402 pull-up on the output of the OD buffer (just in case) and not stuff in the live product.
For example TI has the single gate buffer for $0.03 USD in 1k qty (direct from TI store):
http://www.ti.com/product/SN74LVC1G07/samplebuy
https://www.xcore.com/viewtopic.php?f=3&t=2033
Appears you can configure the GPIO as open drain as you have stated and Dave is showing XC examples of this implementation.
However, best to at least test or leave room for a single gate open-drain buffer in series so that the PCB layout is not wasted if the direct XMOS pin to DAC does not function correctly.
That is, allow for a 0402 or similar 0 ohm to bypass the open drain buffer so that you can stuff either / or to 100% guarantee the design will work. You could even leave room for a 0402 pull-up on the output of the OD buffer (just in case) and not stuff in the live product.
For example TI has the single gate buffer for $0.03 USD in 1k qty (direct from TI store):
http://www.ti.com/product/SN74LVC1G07/samplebuy
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- Experienced Member
- Posts: 77
- Joined: Fri Dec 06, 2013 7:05 pm
thanks, everything seems to tell me it will work out, but i will do as you suggest just in case.