External Flash CS Pin

[Jcvc]

Hi,

Currently, the QSPI CS pin for the external flash is assigned to a 1-bit port. Is there any problem if it instead is assigned to a 4-bit or 8-bit port instead (that 4/8-bit port would not be exclusive for the CS pin)?
I couldn't find any code relating to the QSPI flash, so I assume its only available in the binary format, so that I could read through the code to better understand any possible implications of this change.

Note: I haven't tested yet on the hardware, but before even attempting it, I would like to know if from the software point of view could there be any problem in changing the PIO that is being used as CS pin.

Thank you!

[markp]

The bootrom ROM is hard-wired to use QSPI signals connected to the dedicated ports/pins as documented in the device datasheet.

[Jcvc]

Thanks Mark for the information :)

[Jcvc]

Sorry Mark, but follow-up question: if via hardware I isolate the CS pin of the QSPI IC after booting up, would I be able to then use the XMOS CS pin as a normal 1-bit port?

[markp]

So long as you do not need to use any of our run-time libraries which access flash (such as libquuadflash which is delivered with the Tools for data partition or DFU acccess) I cannot see a reason why the 1-bit port cannot be used as a "normal 1 bit port" with other circuits. Bear in mind, isolation of the flash device has been done with some care - if the device reboots due to watchdog or another async reset, it needs to be able to access the flash to boot. And re isolation the bootrom applies pull-downs to port 4B for 4us and expects read 4'b0000 (boot from QSPI) before then driving/emitting a quad spi read command and receiving a data stream from the flash.