run JTag Boundary scan test on XMOS L2 chip

[Carpentier]

Hello,
This is for a technical question concerning a board that i currently manufacture with :
-XS1-L2 QFN-124 device
-JTAG micro connector
-Ethernet and USB (they is 2 version of the card, one with ethernet and another with USB).

professionnaly designed with a high quality double layer PCB.

XRUN currently work fine.

XFLASH does not work with error "Node 1 configured to boot from flash and no flash device declared for Node 1".


I have configured the mode pins in my card to force boot of Node 0 from flash and boot of node 1 from XMOS LINK.
I use XP-MC-CTRL-L2.xn which is a platform file provided by XMOS and that define a similar boot mode.

Maybe the MODE pins are not correctly soldered on my card. My question is it possible to run a JTAG boundary scan including the MODE pins (not only the IO pins ) and how to run the boundary scan test . what pins are included in the XMOS L2 JTAG boundary scan test.

Thank for any information about JTAG TAP in XMOS L2 device as well as boundary scan testing of MODE pins.

[segher]

XFLASH does not work with error "Node 1 configured to boot from flash and no flash device declared for Node 1".

I have configured the mode pins in my card to force boot of Node 0 from flash and boot of node 1 from XMOS LINK.
I use XP-MC-CTRL-L2.xn which is a platform file provided by XMOS and that define a similar boot mode.

Maybe the MODE pins are not correctly soldered on my card.

As far as I know xflash uses the XN file to determine how the cores boot,
it never looks at the MODE pins.

My question is it possible to run a JTAG boundary scan including the MODE pins (not only the IO pins )

Yes, the mode pins are in the boundary scan.

and how to run the boundary scan test .

Whatever tool you normally use for that.

You'll need to get the BSDL files you need from XMOS.

But, this won't solve the problem you're having, I think; you'll have to
correct your XN file, instead.

[Carpentier]

Some processor (like ARM) at my experience allow everything to be done at all time with only TDI/TDO/TMS/TCK signals. They always respond to JTAG commands in any state (even reset).

The XS1-L has more constraints. Sometime it become 'busy' or 'disabled'. Especially in the case when it boot from an empty or corrupt flash content.

The best way is to connect all signals to the JTAG adapter :
-NRST for a hardware reset
-NJRST and mode pins for a 'Boot wait JTAG' mode

This what have been done in my new processor card and it now works correctly with JTAG tools (xrun and xflash).
What i say is not really sure or proven, but it reflect my experience.

[segher]

Some processor (like ARM) at my experience allow everything to be done at all time with only TDI/TDO/TMS/TCK signals. They always respond to JTAG commands in any state (even reset).

The XS1-L has more constraints. Sometime it become 'busy' or 'disabled'. Especially in the case when it boot from an empty or corrupt flash content.

That is not my experience. The JTAG "just works", as long as you have your
power, clock, reset working correctly of course :-) (some chips do not need
the system clock on for JTAG to work; also, system reset is completely
independent of the TAP on many systems).

I have no idea what "busy" or "disabled" mean... Those are from error
messages from xrun?

[Carpentier]

Let's forget it. Now my card works and connect all the NRST , NJRST and MODE pins to the XTAG.

But i am sure the previous card which did not connect any of this signals to the XTAG (only TDI/TDO/TMS/TCK). failed very much. XRUN failed 30% time with bizarre message like 'core 0 disabled' or 'core 0 busy' and XFLASH never worked saying that it could not fully run flash inquisitor.

This is not a very interesting discussion , but i would recommend any board designer to fully connect the NRST, NJRST and MODE pins(commoned with NJRST ) to their board JTAG header (if any).